* Replace asserts with macros for AArch64, Alpha, LoongArch, Mips, SystemZ inc files.
* Add missing clearing of MCInst
* Ensure correct dir name is used.
* Replace asserts in inc files for PPC, ARM, TriCore
* Replace all asserts in modules with CS_ASSERT.
Also enable the CS_ASSERTs if CMAKE_BUILD_TYPE=Debug
* Formatting
* Fix CID 508418 - Uninitialized struct
* Fix CID 509089 - Fix OOB read and write
* Fix CID 509088 - OOB.
Also adds tests and to ensure no OOB access.
* Fix CID 509085 - Resource leak.
* Fix CID 508414 and companions - Using undefined values.
* Fix CID 508405 - Use of uninitialized value
* Remove unnecessary and badly implemented dev fuzz code.
* Fix CID 508396 - Uninitialzied variable.
* Fix CID 508393, 508365 -- OOB read.
* Fix CID 432207 - OVerlapping memory access.
* Remove unused functions
* Fix CID 432170 - Overlapping memory access.
* Fix CID 166022 - Check for negative index
* Let strncat not depend n src operand.
* Fix 509083 and 509084 - NULL dereference
* Remove duplicated code.
* Initialize sysop
* Fix resource leak
* Remove unreachable code.
* Remove duplicate code.
* Add assert to check return value of cmoack
* Fixed: d should be a signed value, since it is checked against < 0
* Add missing break.
* Add NULL check
* Fix signs of binary search comparisons.
* Add explicit cast of or result
* Fix correct scope of case.
* Handle invalid integer type.
* Return UINT_MAX instead of implicitly casted -1
* Remove dead code
* Fix type of im
* Fix type of d
* Remove duplicated code.
* Add returns after CS_ASSERTS
* Check for len == 0 case.
* Ensure shift operates on uint64
* Replace strcpy with strncpy.
* Handle edge cases for 32bit rotate
* Fix some out of enum warnings
* Replace a strcpy with strncpy.
* Fix increment of address
* Skip some linting
* Fix: set instruction id
* Remove unused enum
* Replace the last usages of strcpy with SStream functions.
* Increase number of allowed AArch64 operands.
* Check safety of incrementing t the next operand.
* Fix naming of operand
* Update python constants
* Fix option setup of CS_OPT_DETAIL_REAL
* Document DETAIL_REAL has to be used with CS_OPT_ON.
* Run Coverity scan every Monday.
* Remove dead code
* Fix OOB read
* Rename macro to reflect it is only used with sstreams
* Fix rebase issues
Disassembling the "slwi", "srwi" and "rldicr" PowerPC instructions
with the "-d" option displays the wrong operands in the detailed
view. This is due to an incorrect break condition in the
"PPC_insert_detail_op_imm_at" function.
This patch fixes#2401.
* Run clang-format
* Remove arm.h header from AArch64 files
* Update all AArch64 module files to LLVM-18.
* Add check if the differs save file is up-to-date with the current files.
* Add new generator for MC test trnaslation.
* Fix warnings
* Update generated AsmWriter files
* Remove unused variable
* Change MCPhysReg type to int16_t as LLVM 18 dictates.
With LLVM 18 the MCPhysReg value's type is changed to int16_t.
If we update modules to LLVM 18, they will generate
compiler warnings that uint16_t* should not be casted to int16_t*.
This makes changing the all tables to int16_t necessary, because the alternative is
to duplicate all MCPhysReg related code. Which is even worse.
* Assign enum values to raw_struct member
* Add printAdrAdrpLabel def
* Add header to regression test files.
* Write files to build dir and ignore more parsing errors.
* Fix parsing of MC test files.
* Reset parser after every block
* Add write and patch header step.
* Add and update MC tests for AArch64
* Fix clang-tidy warnings
* Don't warn about padding issues.
They break automatically initialized structs we can not change easily.
* Fix: Incorrect access of LLVM instruction descriptions.
* Initialize DecoderComplete flag
* Add more mapping and flag details
* Add function to get MCInstDesc from table
* Fix incorrect memory operand access types.
* Fix test where memory was not written, ut only read.
* Attempt to fix Windows build
* Fix 2268
The enum values were different and hence lead to different decoding.
* Refactor SME operands.
- Splits SME operands in Matrix and Predicate operands.
- Fixes general problems of incorrect detections with
the vector select/index operands of predicate registers.
- Simplifies code.
* Fix up typo in WRITE
* Print actual path to struct fields
* Add Registers of SME operands to the reg-read list
* Add tests for SME operands.
* Use Capstone reg enum for comparison
* Fix tests: 'Vector arra...' to 'operands[x].vas'
* Add the developer fuzz option.
* Fix Python bindings for SME operands
* Fix variable shadowing.
* Fix clang-tidy warnings
* Add missing break.
* Fix varg usage
* Brackets for case
* Handle AArch64_OP_GROUP_AdrAdrpLabel
* Fix endian issue with fuzzing start bytes
* Move previous sme.pred to it's own operand type.
* Fix calculation for imm ranges
* Print list member flag
* Fix up operand strings for cstest
* Do only a shallow clone of the cmocka stable branch
* Fix: Don't categorize ZT0 as a SME matrix operand.
* Remove unused code.
* Add flag to distinguish Vn and Qn registers.
* Add all registers to detail struct, even if emitted in the asm text
* Fix: Increment op count after each list member is added.
* Remove implicit write to NZCV for MSR Imm instructions.
* Handle several alias operands.
* Add details for zero alias with za0.h
* Add SME tile to write list if written
* Add write access flags to operands which are zeroed.
* Add SME tests of #2285
* Fix tests with latest syntax changes.
* Fix segfault if memory operand is only a label without register.
* Fix python bindings
* Attempt to fix clang-tidy warning for some configurations.
* Add missing test file (accidentially blocked by gitignore.)
* Print clang-tidy version before linting.
* Update differ save file
* Formatting
* Use clang-tidy-15 as if possible.
* Remove search patterns for MC tests, since they need to be reworked anyways.
* Enum to upper case change
* Add information to read the OSS fuzz result.
* Fix special case of SVE2 operands.
Apparently ZT0 registers can an index attached,
get which is BOUND to it. We have no "index for reg" field.
So it is simply saved as an immediate.
* Handle LLVM expressions without asserts.
* Ensure choices are always saved.
* OP_GROUP enums can't be all upper case because they contain type information.
* Fix compatibility header patching
* Update saved_choices.json
* Allow mode == None in test_corpus
* Add test with ASAN enabled.
* Fix leaks in cstool and cs.c
* Add work around so ASAN binaries don't DEADSIGNAL due to too many randomized address bits.
* Add ASAN build arguments to cstest
* Fix leaks in cstest
* Use cstest binary build by the main build.
* Add clonging step for cmocka when cstest is build
* Skip Python tests for ASAN
* Remove make build from CI
* Fix leaks in cstest.
- Rewrite split to remove leaks and improve runtime by 6%
- Add free()
* Fix cmocka external project to stable branch.
* Revert "Fix leaks in cstest."
This reverts commit bf8ee125b0c58f9c794eb081a69c80f8a71825cd.
* Fix memleaks in cstest
* Document adding of ASAN job to release guide
* Add CAPSTONE_BUILD_CSTEST to build docs
* Fix double free
* Add more detail tests to CI and fix them
* Initialize variables
* Fix typo
* Update cstest build docs
* Revert "Remove make build from CI"
This reverts commit 84f7360c6da6183cd41bec0fef3e1d0a2ee49ddf.
* Make cstest only run for cmake builds.
* Add cstest job for make build.
* Add CAPSTONE_DIET build test.
* Compile the compatibility header test with ASAN if enabled.
* Fix DIET build by excluding not used code.
* Missing "
* Build static library with ASAN and DIET if enabled.
* Revert "Add CAPSTONE_DIET build test."
This reverts commit 71e1469dee53bfdb6b275dd1be19f6eb21a0c023.
Despite being widely implemented and part of C++, the 0b prefix is not
part of any C standard and will be rejected by some compilers such as
Apple GCC 4.0.1 (5493).
There is a compiler bug in latest MSVC, which at the time of writing is
19.36.32535: given `switch (x)`, where `x` is 64 bits wide, the compiler
generates code that computes an incorrect jump table index. E.g. if
`x` is zero, it ends up reading the table entry at index -1.
This has several consequences:
- Branch immediates are memory operands from now. Hence they are added manually as immediate.
- Some operands, handled over printOprerand(), are added to a mem operand, but the mem operand
is never closed. There is simply no indication when a memory operand ends.
So we close the mem operand now always, after an offset or disp awas added and the base exists.
* Add auto-sync updater.
* Update Capstone core with auto-sync changes.
* Update ARM via auto-sync.
* Make changes to arch modules which are introduced by auto-sync.
* Update tests for ARM.
* Fix build warnings for make
* Remove meson.build
* Print shift amount in decimal
* Patch non LLVM register alias.
* Change type of immediate operand to unsiged (due to: #771)
* Replace all occurances of a register with its alias.
* Fix printing of signed imms
* Print rotate amount in decimal
* CHange imm type to int64_t to match LLVM imm type.
* Fix search for register names, by completing string first.
* Print ModImm operands always in decimal
* Use number format of previous capstone version.
* Correct implicit writes and update_flags according to SBit.
* Add missing test for RegImmShift
* Reverse incorrect comparision.
* Set shift information for move instructions.
* Set mem access for all memory operands
* Set subtracted flag if offset is negative.
* Add flag for post-index memory operands.
* Add detail op for BX_RET and MOVPCLR
* Use instruction post_index operand.
* Add VPOP and VPUSH as unique CS IDs.
* Add shifting info for MOVsr.
* Add TODOs.
* Add in LLVM hardcoded operands to detail.
* Move detail editing from InstPrinter to Mapping
* Formatting
* Add removed check.
* Add writeback register and constraints to RFEI instructions.
* Translate shift immediate
* Print negative immediates
* Remove duplicate invalid entry
* Add CS groups to instructions
* Fix write attriutes of stores.
* Add missing names of added instructions
* Fix LLVM bug
* Add more post_index flags
* http -> https
* Make generated functions static
* Remove tab prefix for alias instructions.
* Set ValidateMCOperand to NULL.
* Fix AddrMode3Operand operands
* Allow getting system and banked register name via API
* Add writeback to STC/LDC instructions.
* Fix (hopefully) last case where disp is negative and subtracted = true
* Remove accidentially introduced regressions
Because the cs_insn->mnemonic gets set *after* the
post_printer is called and cs_insn->mnemonic is not memset to 0
before, post_printer() of PPC receives a cs_insn->mnemonic with
random data.
This in turn leads randomly to incorrect setting of the branch hints
and the update_cr0 flag. Because those are set in the post_printer()
of PPC.
* Constify registerinfo.py output
Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify instrinfo-arch.py output
In this case, do not actively strip const.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the AArch64 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the EVM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M680X backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M68K backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Mips backend
The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like. Just apply
the fixes to the tables by hand for now.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Sparc backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the TMS320C64x backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the X86 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the XCore backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify systemregister.py output
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the ARM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the PowerPC backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the MOS65XX backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the SystemZ backend
The mapping of system register to indexes is easy to
generate read-only. Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the WASM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify cs.c
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the BPF backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
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