Commit Graph

3942 Commits

Author SHA1 Message Date
Nguyen Anh Quynh d553dbf3eb python: raise CsError(CS_ERR_SKIPDATA) when accessing irrelevant data in skipdata mode. this fixes issue #679 2018-07-18 13:37:45 +08:00
Nguyen Anh Quynh 9ea5fbd210 ChangeLog for v3.0.5 2018-07-17 15:59:51 +08:00
Nguyen Anh Quynh 4741517c34 change PKG_TAG for v3.0.5 2018-07-17 15:30:42 +08:00
keenk d03cab449d Update TestX86.java (#1208)
* Fix java bindings for encoding

Fix java bindings broken with addition of encoding struct in #1194

* Add files via upload


Update TestX86.java for printing encoding struct and register access

* Add files via upload

Added conditions to only print encoding class info when needed.
Formatting.

* Add files via upload

Another space
2018-07-13 15:52:19 +07:00
clslgrnc 9b9844d276 Init cs_detail (#1205)
* Update init of cs_detail for AArch64

as @aquynh requested in #1125

* Update init of cs_detail for ARM

as @aquynh requested in #1125

* Update init of cs_detail for EVM

as @aquynh requested in #1125

* Update init of cs_detail for M680X

as @aquynh requested in #1125

* Update init of cs_detail for M68K

as @aquynh requested in #1125

* Update init of cs_detail for Mips

as @aquynh requested in #1125

* Update init of cs_detail for PowerPC

as @aquynh requested in #1125

* Update init of cs_detail for Sparc

as @aquynh requested in #1125

* Update init of cs_detail for SystemZ

as @aquynh requested in #1125

* Update init of cs_detail for TMS320C64x

as @aquynh requested in #1125

* Update init of cs_detail for XCore

as @aquynh requested in #1125

* Comment on init of cs_detail

* wrap long lines
2018-07-12 11:01:34 +07:00
Nguyen Anh Quynh 728e6999eb x86: fix imm operand of RETF. see #1204 2018-07-11 23:20:00 +08:00
Martin b5b2a11474 readDisplacement fix (#1200) 2018-07-11 23:19:45 +08:00
Martin cc7b088236 readDisplacement fix (#1200) 2018-07-11 22:18:38 +07:00
Nguyen Anh Quynh ae703aaea0 x86: fix imm operand of RETF. see #1204 2018-07-11 23:12:18 +08:00
keenk e90af81ac8 Fix java bindings for encoding (#1202)
Fix java bindings broken with addition of encoding struct in #1194
2018-07-09 08:26:33 +07:00
Nguyen Anh Quynh ec8a5ce98f Merge branch 'next' of github.com:aquynh/capstone into next 2018-07-05 11:34:32 +08:00
Nguyen Anh Quynh ddfd659582 evm: default case for switch 2018-07-05 11:33:39 +08:00
Nguyen Anh Quynh ee12da07ed evm: cleanup group_name_maps[] 2018-07-05 11:32:42 +08:00
Nguyen Anh Quynh 8313b16f2d evm: fix bug introduced in some recent fixes 2018-07-05 11:32:19 +08:00
Nguyen Anh Quynh f5b2ac1c29 evm: cleanup 2018-07-05 11:32:05 +08:00
Nguyen Anh Quynh 14db64b863 evm: simplify EVM_get_insn_id() 2018-07-05 11:31:53 +08:00
Nguyen Anh Quynh 0f5bbca5d9 evm: correct comments on evm_insn_find() 2018-07-05 11:31:39 +08:00
Nguyen Anh Quynh c5c7d4fc43
evm: fix header guard in EVMModule.c 2018-07-05 01:16:24 +08:00
Nguyen Anh Quynh cd447b2393 x86: X86_immediate_size() returns uint8 2018-07-04 23:02:22 +08:00
Nguyen Anh Quynh 3fef42f345 coding style 2018-07-04 22:54:14 +08:00
Nguyen Anh Quynh 5009a506ba CREDITS.TXT 2018-07-04 22:50:28 +08:00
Stephen Eckels dce7da98f8 Merges encoding to next (#1194)
* merge encoding branch into next branch

* added python bindings and updated test to support encoding

* fix python import

* fix py binding fields

* fix disp size printing

* fixed py binding, again

* Update CREDITS.TXT

* fixed formatting and a cast

* Changed param from int to uint8_t, fixed warnings
2018-07-04 22:47:55 +08:00
Nguyen Anh Quynh 3f9978c809 Revert "Merges encoding branch (#1187)"
This reverts commit a1ed8fc6f6.
2018-07-03 11:55:29 +08:00
Catena cyber 0aa4e76b8e Initializes to 0 X86 immediateOffset (#1192) 2018-06-29 17:00:51 +08:00
Catena cyber a31b532864 Initializes to 0 X86 immediateOffset (#1192) 2018-06-29 16:59:30 +08:00
Stephen Eckels a1ed8fc6f6 Merges encoding branch (#1187)
* Added encoding field to instructions, as per encoding branch

The encoding branch appears to have added some useful fields
accessible from the public API, including the size and offsets
of displacements and immediates in instructions.  I needed access
to these fields, but the encoding branch is months behind the
active branches, so I took the minimum code from the old encoding
branch and put them into a more recent version of master.

It does seem that the most recent version does not have an offset
for the modRM byte in the InternalInstruction struct, so I did
not keep this field when bringing it to the more recent version.

I also added some of the changes made by user jellever, who added
support for accessing these new fields from the python bindings.

(cherry picked from commit d358c4b987cc77af90e24da15937e021c42f682f)

* Fixed bug with python bindings from adding encoding field

I had forgotten an import that resulted in failure when trying
to obtain instruction details.

(cherry picked from commit 44a15e378900efb624e7cdb952d32558ba0de684)

* promoted displacement to 64 bits

* Added modrm offset

* formatting from review fixed

* updated 32 bit C tests

* Added 64 and 16 bit C tests

* Updated python tests

* fixed formatting and size in py bindings

* Delete Solution.VC.db-shm

* Delete Solution.VC.db-wal

* Update test_x86.c

* fixed formatting and conditional prints

* fixed formatting
2018-06-28 21:37:34 +08:00
Nguyen Anh Quynh 84fc70836d CREDITS.TXT 2018-06-25 19:57:50 +08:00
Catena cyber c956cc0631 Better error reporting for python binding (#1189) 2018-06-25 19:48:02 +08:00
Catena cyber 2c06f114b9 Initialize X86 necessaryPrefixLocation (#1179)
* Initialize X86 necessaryPrefixLocation

* necessaryPrefixLocation initialization to -1

* Revert "necessaryPrefixLocation initialization to -1"

This reverts commit 04fc4b6702ad839d87ee4f73695b9dfc632fb698.
2018-06-25 19:46:58 +08:00
Catena cyber 7efdd25b54 Initialize X86 necessaryPrefixLocation (#1179)
* Initialize X86 necessaryPrefixLocation

* necessaryPrefixLocation initialization to -1

* Revert "necessaryPrefixLocation initialization to -1"

This reverts commit 04fc4b6702ad839d87ee4f73695b9dfc632fb698.
2018-06-25 19:46:04 +08:00
Catena cyber 60ca025dd8 Better error reporting for python binding (#1188)
To diagnose issue with oss-fuzz building corpus
2018-06-25 01:35:59 +08:00
Travis Finkenauer 65da43d0b1 Declare global arch arrays with contents (next branch) (#1186)
* Declare global arch arrays with contents (#1171)

This eliminates the need for archs_enable() and eliminates the racey
initialization.

This makes the architecture-specific init and option functions
non-static so that they may be called from a different file.

Cherry-picked 853a2870

* Add cs_arch_disallowed_mode_mask global

Cherry-pick 94bce437:
mips: CS_MODE_MIPS32R6 implies CS_MODE_32

Cherry-pick 8998a3a1:
ppc: fix endian check (#1029)
Fixes bug where endianness could not be set for ppc.

Remove `big_endian` field of `cs_struct`.
Added a helper macro `MODE_IS_BIG_ENDIAN()` to check if
`CS_MODE_BIG_ENDIAN` is set.

Refactored `cs_open()` check for valid mode out of arch-specific code
into arch-independent code. Also added a valid mode check to
`cs_option()`.  The checks use a new global array
`cs_arch_disallowed_mode_mask[]`.

* Make global arrays static

Make all_arch uint32_t to guarantee a certain number of bits (with
adequate room for growth).
2018-06-24 21:05:04 +08:00
Nguyen Anh Quynh 0b874b2fca cleanup 2018-06-22 01:03:26 +08:00
Travis Finkenauer 853a2870ce Declare global arch arrays with contents (#1171)
This eliminates the need for archs_enable() and eliminates the racey
initialization.

This makes the architecture-specific init, option, and destroy functions
non-static so that they may be called from a different file.
2018-06-21 14:52:35 +08:00
Nguyen Anh Quynh ba25ab0fe1 Java: pump number of Mips operands to 10. see #1183 2018-06-19 09:36:38 +08:00
Nguyen Anh Quynh 718bad8b5b Python: pump number of Mips operands to 10. see #1183 2018-06-19 09:35:37 +08:00
Catena cyber 4267f2619a Extends Mips number of operands (#1183)
for CS_MODE_MIPS32R6
2018-06-19 09:33:47 +08:00
Catena cyber bcb1247b10 Builds a test corpus for fuzzing (#1184)
* Limit size of inputs for fuzz targets

* Build a test corpus for fuzzing
2018-06-19 09:31:50 +08:00
Catena cyber 1958fe83c7 SystemZ MIN_INT right print (#1182) 2018-06-16 23:09:25 +01:00
Catena cyber dd82c3a88a EVM fuzz fixes (#1181)
Sets id to instruction
Completes missing set and enforces number of instructions
2018-06-16 22:35:02 +01:00
Catena cyber ad88f6c24e EVM initialize regs_read and regs_write (#1180) 2018-06-15 23:15:12 +01:00
vit9696 36d4585566 Add Availability.h include to fix macOS SDK instrinsics 2018-06-15 22:14:48 +08:00
vit9696 7723175e80 Add Availability.h include to fix macOS SDK instrinsics (#1175) 2018-06-14 22:12:26 +01:00
vit9696 856b207010 Refactor confusing if for xacquire/xrelease (#1173)
Sync with https://github.com/llvm-mirror/llvm/blob/7cdce81/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp#L362
2018-06-13 23:04:20 +01:00
vit9696 946fe47170 macOS kernel has no limits.h but i386/limits.h (#1172) 2018-06-13 22:59:39 +01:00
Catena cyber b8c7cd8943 Builds a test corpus for fuzzing (#1174)
Modifies the list of architectures and modes fuzzed
2018-06-13 22:58:40 +01:00
vit9696 f7706942b5 Refactor confusing if for xacquire/xrelease (#1173)
Sync with https://github.com/llvm-mirror/llvm/blob/7cdce81/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp#L362
2018-06-13 22:14:53 +08:00
vit9696 dc59d17b91 macOS kernel has no limits.h but i386/limits.h (#1172) 2018-06-13 22:14:19 +08:00
Catena cyber 04a6d4022c Adds a size limit for inputs to fuzz target (#1167) 2018-06-07 01:40:47 +08:00
Catena cyber 2b054af693 Use printint functions from SStream (#1165)
in perticular, not to overflow -INT_MIN
2018-06-06 06:31:53 +08:00