Commit Graph

7 Commits

Author SHA1 Message Date
Andelf 3060117630
Apply new EVM opcode updates (#2602)
* evm: apply new opcode updates and add test cases

* evm: use predefined invalid opcode 0xfe

* python: add CsInsn.is_invalid_insn to bypass evm issue
2025-01-28 20:51:43 +08:00
Richard Henderson 936dca0e2d Constify backends (#1549)
* Constify registerinfo.py output

Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify instrinfo-arch.py output

In this case, do not actively strip const.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the AArch64 backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the EVM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify M680X backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify M68K backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the Mips backend

The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like.  Just apply
the fixes to the tables by hand for now.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the Sparc backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the TMS320C64x backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the X86 backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the XCore backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify systemregister.py output

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the ARM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the PowerPC backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the MOS65XX backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the SystemZ backend

The mapping of system register to indexes is easy to
generate read-only.  Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the WASM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify cs.c

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the BPF backend

Signed-off-by: Richard Henderson <rth@twiddle.net>
2019-12-23 20:30:57 +08:00
clslgrnc 91601ac1fd Init cs_detail (#1205)
* Update init of cs_detail for AArch64

as @aquynh requested in #1125

* Update init of cs_detail for ARM

as @aquynh requested in #1125

* Update init of cs_detail for EVM

as @aquynh requested in #1125

* Update init of cs_detail for M680X

as @aquynh requested in #1125

* Update init of cs_detail for M68K

as @aquynh requested in #1125

* Update init of cs_detail for Mips

as @aquynh requested in #1125

* Update init of cs_detail for PowerPC

as @aquynh requested in #1125

* Update init of cs_detail for Sparc

as @aquynh requested in #1125

* Update init of cs_detail for SystemZ

as @aquynh requested in #1125

* Update init of cs_detail for TMS320C64x

as @aquynh requested in #1125

* Update init of cs_detail for XCore

as @aquynh requested in #1125

* Comment on init of cs_detail

* wrap long lines
2018-07-12 11:01:34 +07:00
Nguyen Anh Quynh 68d4e771eb evm: default case for switch 2018-07-05 11:33:39 +08:00
Catena cyber 204be7951d EVM fuzz fixes (#1181)
Sets id to instruction
Completes missing set and enforces number of instructions
2018-06-16 22:35:02 +01:00
Catena cyber 63ff398094 EVM initialize regs_read and regs_write (#1180) 2018-06-15 23:15:12 +01:00
Nguyen Anh Quynh 1da2ae94de EVM: add missing files 2018-03-31 17:32:22 +08:00