* Fix access bug for TEST op
Results for TEST instructions are discarded hence operands should have
no write access.
* Fix access bug for TEST (reduce)
* trigger new ci test
---------
Co-authored-by: kabeor <1597915586@qq.com>
* Fix a few registry access mode mappings
* Fix rollback of operand access changes
Re-fix operand access of three mov instructions
* Remove binding breaking #if 0
The python script for generating constants in the bindings does not know how to handle the #if 0 statements included in these files.
* Add files via upload
Update registry access mode for several versions of pop such as POPDS, POPSS, etc
* Fix a few registry access mode mappings
* Fix rollback of operand access changes
Re-fix operand access of three mov instructions
* Remove binding breaking #if 0
The python script for generating constants in the bindings does not know how to handle the #if 0 statements included in these files.
* Updated registry access on cmov instructions
Registry access for the destination operand of the conditional move (cmov) opcodes were incorrectly listed as READ | WRITE. Although you would expect the two operands to be compared in this opcode, it instead relies on the associated flag in EFLAGS regardless of the value in the destination operand.
* Constify registerinfo.py output
Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify instrinfo-arch.py output
In this case, do not actively strip const.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the AArch64 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the EVM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M680X backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M68K backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Mips backend
The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like. Just apply
the fixes to the tables by hand for now.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Sparc backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the TMS320C64x backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the X86 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the XCore backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify systemregister.py output
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the ARM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the PowerPC backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the MOS65XX backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the SystemZ backend
The mapping of system register to indexes is easy to
generate read-only. Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the WASM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify cs.c
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the BPF backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
