Commit Graph

3762 Commits

Author SHA1 Message Date
Catena cyber 950476606b Initialize X86 necessaryPrefixLocation (#1179)
* Initialize X86 necessaryPrefixLocation

* necessaryPrefixLocation initialization to -1

* Revert "necessaryPrefixLocation initialization to -1"

This reverts commit 04fc4b6702ad839d87ee4f73695b9dfc632fb698.
2018-06-25 19:46:58 +08:00
Catena cyber 27a169e305 Initialize X86 necessaryPrefixLocation (#1179)
* Initialize X86 necessaryPrefixLocation

* necessaryPrefixLocation initialization to -1

* Revert "necessaryPrefixLocation initialization to -1"

This reverts commit 04fc4b6702ad839d87ee4f73695b9dfc632fb698.
2018-06-25 19:46:04 +08:00
Catena cyber 154c9ffdd8 Better error reporting for python binding (#1188)
To diagnose issue with oss-fuzz building corpus
2018-06-25 01:35:59 +08:00
Travis Finkenauer 292116bd0d Declare global arch arrays with contents (next branch) (#1186)
* Declare global arch arrays with contents (#1171)

This eliminates the need for archs_enable() and eliminates the racey
initialization.

This makes the architecture-specific init and option functions
non-static so that they may be called from a different file.

Cherry-picked 853a2870

* Add cs_arch_disallowed_mode_mask global

Cherry-pick 94bce437:
mips: CS_MODE_MIPS32R6 implies CS_MODE_32

Cherry-pick 8998a3a1:
ppc: fix endian check (#1029)
Fixes bug where endianness could not be set for ppc.

Remove `big_endian` field of `cs_struct`.
Added a helper macro `MODE_IS_BIG_ENDIAN()` to check if
`CS_MODE_BIG_ENDIAN` is set.

Refactored `cs_open()` check for valid mode out of arch-specific code
into arch-independent code. Also added a valid mode check to
`cs_option()`.  The checks use a new global array
`cs_arch_disallowed_mode_mask[]`.

* Make global arrays static

Make all_arch uint32_t to guarantee a certain number of bits (with
adequate room for growth).
2018-06-24 21:05:04 +08:00
Nguyen Anh Quynh 7566f79879 cleanup 2018-06-22 01:03:26 +08:00
Travis Finkenauer ce597d5296 Declare global arch arrays with contents (#1171)
This eliminates the need for archs_enable() and eliminates the racey
initialization.

This makes the architecture-specific init, option, and destroy functions
non-static so that they may be called from a different file.
2018-06-21 14:52:35 +08:00
Nguyen Anh Quynh 618676a229 Java: pump number of Mips operands to 10. see #1183 2018-06-19 09:36:38 +08:00
Nguyen Anh Quynh b6e566b726 Python: pump number of Mips operands to 10. see #1183 2018-06-19 09:35:37 +08:00
Catena cyber d3c7fd57e7 Extends Mips number of operands (#1183)
for CS_MODE_MIPS32R6
2018-06-19 09:33:47 +08:00
Catena cyber b22f425799 Builds a test corpus for fuzzing (#1184)
* Limit size of inputs for fuzz targets

* Build a test corpus for fuzzing
2018-06-19 09:31:50 +08:00
Catena cyber 9ecaeea75a SystemZ MIN_INT right print (#1182) 2018-06-16 23:09:25 +01:00
Catena cyber 204be7951d EVM fuzz fixes (#1181)
Sets id to instruction
Completes missing set and enforces number of instructions
2018-06-16 22:35:02 +01:00
Catena cyber 63ff398094 EVM initialize regs_read and regs_write (#1180) 2018-06-15 23:15:12 +01:00
vit9696 c2514aab00 Add Availability.h include to fix macOS SDK instrinsics 2018-06-15 22:14:48 +08:00
vit9696 f52aa1f39c Add Availability.h include to fix macOS SDK instrinsics (#1175) 2018-06-14 22:12:26 +01:00
vit9696 a31ffb343f Refactor confusing if for xacquire/xrelease (#1173)
Sync with https://github.com/llvm-mirror/llvm/blob/7cdce81/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp#L362
2018-06-13 23:04:20 +01:00
vit9696 c0943009a9 macOS kernel has no limits.h but i386/limits.h (#1172) 2018-06-13 22:59:39 +01:00
Catena cyber d2e82d0c44 Builds a test corpus for fuzzing (#1174)
Modifies the list of architectures and modes fuzzed
2018-06-13 22:58:40 +01:00
vit9696 f8eae0ac15 Refactor confusing if for xacquire/xrelease (#1173)
Sync with https://github.com/llvm-mirror/llvm/blob/7cdce81/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp#L362
2018-06-13 22:14:53 +08:00
vit9696 6625328843 macOS kernel has no limits.h but i386/limits.h (#1172) 2018-06-13 22:14:19 +08:00
Catena cyber 41da47b213 Adds a size limit for inputs to fuzz target (#1167) 2018-06-07 01:40:47 +08:00
Catena cyber aad3aca3e7 Use printint functions from SStream (#1165)
in perticular, not to overflow -INT_MIN
2018-06-06 06:31:53 +08:00
Catena cyber a33567db49 Fix ARM operand subtracted field (#1163) 2018-06-06 06:17:25 +08:00
Catena cyber 9217582b9f Fixes shift for ARM memory operand (#1162)
Shift is for same operand as index register
2018-06-06 06:09:53 +08:00
Catena cyber 62f1d9fe14 Fix ARM operand subtracted field (#1163) 2018-06-05 22:20:02 +08:00
Catena cyber d15e310112 Fix integer overflow on systemz (#1164)
using fixed function from SStream.c
2018-06-05 14:03:55 +08:00
Catena cyber 8f7c495e05 Fix undefined shifts (#1158) 2018-06-03 22:29:58 +08:00
Catena cyber 7e79f507a0 fix undefined shift in countLeadingZeros (#1157) 2018-06-03 22:27:54 +08:00
Catena cyber fd435a861b fix undefined shift in countLeadingZeros (#1157) 2018-06-03 22:26:11 +08:00
Catena cyber 17076b66d2 Fix undefined negative value shift (#1161)
Use multiply instead
2018-06-03 22:19:07 +08:00
Nguyen Anh Quynh 8dacad7911 code style 2018-06-02 22:22:56 +08:00
Nguyen Anh Quynh 450a779f2f code style 2018-06-02 22:22:26 +08:00
Catena cyber 5f5ed3f6e6 operands are invalid at initialisation (#1149) 2018-06-02 22:21:09 +08:00
Catena cyber 0b3136e7fe Print right hex value for MIN_INT (#1160) 2018-06-02 22:20:13 +08:00
Catena cyber 93ba399855 Print right hex value for MIN_INT (#1155) 2018-06-02 16:55:05 +08:00
Catena cyber fbb90bcb35 Fix undefined shifts (#1158)
Use multiply instead
Found by oss-fuzz
2018-06-02 16:52:52 +08:00
Catena cyber de55611538 operands are invalid at initialisation (#1159)
Found by oss-fuzz
2018-06-02 16:52:24 +08:00
Catena cyber 65c0be823c Fix undefined shifts (#1156)
* Fix undefined shifts

Found by oss-fuzz
uint8_t gets promoted to integer
and integers shift cannot overflow on sign bit

* Fix undefined shifts

shifting 31 bits the sign bit
2018-06-02 16:51:40 +08:00
Catena cyber bf97c62001 Undefined shifts (#1154)
* Fix undefined shifts

uint8 gets promoted to signed integer

in ARM, MIPS, Sparc
in AArch64, PPC and Xcore

* fix undefined shift in powerpc

* Fix undefined shift in Mips

use mulitply instead
2018-06-02 16:49:36 +08:00
Catena cyber 6c796d996b We can read more registers from M68K (#1151) 2018-06-02 01:08:54 +08:00
Nguyen Anh Quynh e404d81514 Merge branch 'next' of github.com:aquynh/capstone into next 2018-06-01 22:58:36 +08:00
Nguyen Anh Quynh aeb4128cab x86: support new instructions endbr64 & endbr32 2018-06-01 22:57:53 +08:00
Catena cyber 99e78c9f9e Adds Philippe Antoine (Catena cyber) to credits (#1153) 2018-06-01 22:41:17 +08:00
Catena cyber e42083410b Fuzz next branch (#1152) 2018-06-01 22:30:53 +08:00
Nguyen Anh Quynh e1494cf1f4 cleanup 2018-06-01 22:05:50 +08:00
Nguyen Anh Quynh ec3705d8fd Merge branch 'next' of https://github.com/aquynh/capstone into next 2018-06-01 22:04:13 +08:00
clslgrnc c3527b72e1 Improve init of cs_detail for x86 (#1125) 2018-06-01 22:03:55 +08:00
Catena cyber f1f5fca1b5 M68K increment index after having written register (#1147) 2018-06-01 20:53:01 +08:00
Catena cyber d937c94cac Fix buffer overflow in M68K (#1146) 2018-06-01 20:52:37 +08:00
Catena cyber 7c668dac9d Do not shift signed values in Mips disassembling (#1148)
* Do not shift signed values in Mips disassembling

* Do not shift signed values in Mips disassembling

Multiply instead
2018-06-01 20:51:46 +08:00