19ee2d10b3
inttypes.h fix
2015-03-29 21:16:38 +08:00
efffe787d1
Add new API and start to provide access information for instruction operands
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- New API cs_regs_access() that provide registers being read & modified by instruction
- New field cs_x86_op.access provides access info (READ, WRITE) for each operand
- New field cs_x86.eflags provides EFLAGS affected by instruction
- Extend cs_detail.{regs_read, regs_write} from uint8_t to uint16_t type
2015-03-25 15:02:13 +08:00
75e94a06c9
arm: fix some instructions in insn_ops[] where GPRwithAPSR & addr_offset_non should be considered for register access. issue reported by @derrekr
2015-03-23 00:56:03 +08:00
5e5b1f5366
core: rename operand access symbols from CS_OP_* to CS_AC_*
2015-03-23 00:09:20 +08:00
6a77cc7463
arm: some fixes for insn_ops[] where some registers should be considered for accessing. issue reported by @derrek
2015-03-22 23:24:30 +08:00
c79a8a03c4
arm: fix lots of issues with insn_op[], and move it to a separate file ARMMappingInsnOp.inc
2015-03-22 13:39:54 +08:00
ba7bf10dbb
Merge pull request #278 from radare/arm-priv
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add ARM_GRP_PRIVILEGE group and tag some instructions
2015-03-12 17:41:52 +08:00
e17124356e
arm: add the missing Virtualization group to group_name_maps[]. bug reported by Coverity
2015-03-12 00:26:08 +08:00
fcde1e190a
Merge branch 'next' of https://github.com/aquynh/capstone into next
2015-03-11 10:28:49 +08:00
21b0bdd0e1
Fix indent issue
2015-03-11 00:40:14 +01:00
cf74a14b43
add ARM_GRP_PRIVILEGE group and tag some instructions
2015-03-11 00:13:53 +01:00
6791b268c4
arm: revert the last change on OperandInfo* in ARMGenInstrInfo.inc
2015-03-10 16:52:22 +08:00
dfd1c0b44e
arm: get rid of some useless variables in ARMGenInstrInfo.inc. this saves at lease 50KB
2015-03-10 15:21:22 +08:00
bb5dccedfa
core: put insns[] into separate .inc files to make it easier to manage
2015-03-08 10:54:32 +08:00
e0329ddde3
arm: printModImmOperand() should print Imm as unsigned number in some special cases
2015-03-08 00:29:20 +08:00
8e343885be
arm: update insn_ops[]
2015-03-07 16:38:35 +08:00
b8b83482b7
arm: print immediate in hex format when suitable for printModImmOperand()
2015-03-07 00:26:24 +08:00
bfcaba5851
2015
2015-03-04 17:45:23 +08:00
2c55b81f06
mips: fix conflict when merging with 'next' branch
2015-03-04 11:29:49 +08:00
3973d8b11e
Silencing Clang warning bys casting values
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Warnings were: "Implicit conversion loses integer precision: 'size_t' to 'cs_mode'/'cs_opt_value'"
2015-03-04 11:26:27 +08:00
7e25609ad3
arm: fix bugs in the last commit
2015-03-03 18:28:10 +08:00
d1fc2bd3b9
arm: update core
2015-03-03 16:26:32 +08:00
c87ccd1b89
mips: fix bugs in the last update
2015-03-02 17:31:44 +08:00
96ee76fa2a
Merge branch 'next' of https://github.com/radare/capstone into test2
2015-02-28 08:29:21 +08:00
4b68d9505e
arm: fix some warnings reported by MSVC
2015-02-25 18:02:19 +08:00
9f4b373f56
arm: fix some instructions in insn_ops[]
2015-02-24 18:38:56 +08:00
9c10ace558
Make pkg-config and source consistent with installation
2015-02-24 05:03:04 +01:00
4c5039582b
arm: fix bugs in the last commit where some instructions in insn_ops[] do not update CPSR
2015-02-24 09:19:25 +08:00
10434df006
arm: some instructions update status flags in insns_ops[]
2015-02-24 08:58:22 +08:00
760c5486d2
arm: fix some more Thumb & vectored instructions in insn_ops[]
2015-02-24 00:16:03 +08:00
cea230f867
arm: fix some Thumb instructions in insn_ops[]
2015-02-23 23:56:40 +08:00
d0f96df26d
arm: add insn_ops[] (temporarily disable)
2015-02-23 23:50:15 +08:00
ced9a6ed92
Correct printAM3PreOrOffsetIndexOp disp value
2015-02-15 22:41:20 +08:00
ec95020fa0
Remove incorrect ITBlock.size = 0
2015-02-15 09:33:39 +08:00
58fbf2f627
arm: add few more post-indexed instructions doing writeback
2015-01-21 12:25:36 +08:00
5719eb5a9d
arm: fix a bug in the last commit
2015-01-21 12:16:15 +08:00
03e5e106b0
arm: some load/store instructions writeback without bang letter. bug reported by @jabba2989
2015-01-21 12:15:14 +08:00
67fe1c2547
arm: in Thumb mode, ADC & SBC do not update flags. bug reported by @jabba2989
2015-01-13 22:17:37 +08:00
706b808af3
arm: add lshift field to arm_op_mem to provide left-shift value for index register in some memory op. issue reported by @jabba2989
2015-01-12 15:27:29 +08:00
bda2c1c591
arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP.
2014-12-29 17:20:19 +01:00
0f9ef1559d
arm: BL & BLX do not read SP, but PC register. issue reported by Der Rek
2014-12-27 16:16:12 +08:00
3caf837c9a
arm: alias LDR instruction with operands '[sp], 4' to POP. suggested by Pancake
2014-11-27 14:34:40 +08:00
a2934a7b6a
arm: print immediate op of MVN instruction in positive hexadecimal form. issue reported by Pancake
2014-11-25 21:02:18 +08:00
c00bc2efb6
fix the left-over C89 issues introduced by Pedro
2014-11-21 19:29:47 +08:00
68197d9a5e
Make it C89 compatible.
2014-11-20 13:45:43 +00:00
202da41980
Fix compiler warnings about different sizes and sign.
2014-11-20 12:13:19 +00:00
1ffc1b2201
arm: fix printMemBOption() that was wrongly fixed in 51888c3e08
2014-11-12 13:33:15 +08:00
51888c3e08
arm: fix some bugs reported by VS2010. thanks Axel for testing
2014-11-11 23:59:23 +08:00
8cdafda551
arm: add new field mem_barrier to cs_arm struct. this requires changes in bindings
2014-11-11 22:30:30 +08:00
278e7270d9
arm: print immediate in positive form for AND/ORR/EOR/BIC instructions
2014-11-11 12:50:43 +08:00
Cr4sh