Nguyen Anh Quynh
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eb4dcfb214
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arm: sync with llvm 7.0.1
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2019-03-16 15:22:15 +08:00 |
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Nguyen Anh Quynh
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bfcaba5851
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2015
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2015-03-04 17:45:23 +08:00 |
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Nguyen Anh Quynh
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04d9f8ee17
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arm: update core with a lot more details provided in detail mode now. update Python & Java bindings to reflect the core's changes
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2014-09-01 23:27:24 +08:00 |
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Nguyen Anh Quynh
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f721e3124d
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Disassembler -> Disassembly
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2014-05-27 10:45:58 +08:00 |
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Nguyen Anh Quynh
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6456481508
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x86: add immediate operand (1) for SHL/SHR/ROR/ROL/SAR/SAL in detail mode & Intel syntax
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2014-05-19 16:46:31 +08:00 |
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Nguyen Anh Quynh
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2ff665ad4a
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arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')
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2014-03-11 00:18:50 +08:00 |
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Nguyen Anh Quynh
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4d3e852fbb
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detail option: provide instruction id even when detail option is OFF
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2013-12-14 10:45:09 +08:00 |
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Nguyen Anh Quynh
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a01d1546d6
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x86: handle outs instruction in 16bit mode
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2013-12-12 15:54:30 +08:00 |
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pancake
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f0e4eed89d
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Use const on all read-only buffers
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2013-12-11 22:14:42 +01:00 |
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Nguyen Anh Quynh
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26ee41aa67
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initial import
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2013-11-27 12:11:31 +08:00 |