7 Commits

Author	SHA1	Message	Date
billow	568d179f85	Update tests and inc files ... with llvm-capstone 78180b63f827ee38e23375e7a00825e848aa6956	2023-07-01 16:26:54 +08:00
Anton Kochkov	7b6736ac3e	Convert Tricore tests to Intel register syntax	2023-06-28 21:57:50 +08:00
billow	554133e5c4	feat: Update TriCore processor support and architecture modes ... - Add support for TRICORE architecture modes 110, 120, 130, 131, 160, 161, and 162 in test_corpus.py - Change the TriCore mode from `CS_MODE_TRICORE` to `CS_MODE_TRICORE_162` in `Tricore/*.s.cs`	2023-04-14 00:35:48 +08:00
billow	c9d8d6c9bf	unique tests	2023-04-14 00:35:23 +08:00
billow	5b7e20ad55	fix: TriCore Instruction Formats and Printing ... - Add new operand type `off18imm` - Add `printOff18Imm` function for printing specific immediate value	2023-04-14 00:35:19 +08:00
billow	9bdd734d0e	fix: TriCore instruction decoding and printing. ... - Modify TriCore instructions to use bracket syntax and offsets for better clarity - Add off4_fixup and printSExtImm_n	2023-04-14 00:35:17 +08:00
billow	a78a46a397	fix: TriCore architecture disassembly codes ... - Rename `ISLR_post_increment` to `ISLR_pos` for clarity - Fix register decoding for TriCore architecture in `TriCoreDisassembler.c` - Add new file `LoadStore.s.cs` to `suite/MC/TriCore`	2023-04-14 00:35:16 +08:00