4b4a848027
Print EFLAGS and FPU_FLAGS correctly in test_x86 ( #1365 )
...
* Print EFLAGS and FPU_FLAGS correctly in test_x86
Since the eflags and fpu_flags are union the instruction group needs
to be checked for FPU to see if the flag is an FPU flag. cstool_x86
was already doing this but test_x86 was not. The result was the fadd
instruction from the x86 16bit test was showing in the test_x86
output as having eflags. Since fadd is an fpu instruction the FPU_FLAGS
should be shown instead.
* Remove extra newline in instruction output
All of the other test_<arch>.c functions print a single newline after
the dissassembly. x86 had two newlines. This makes test_x86
consistent with all the other test output.
2019-02-05 09:43:04 +08:00
2fc852dcbd
fix warnings on const char * discards qualifiers
2018-07-24 01:41:59 +08:00
dce7da98f8
Merges encoding to next ( #1194 )
...
* merge encoding branch into next branch
* added python bindings and updated test to support encoding
* fix python import
* fix py binding fields
* fix disp size printing
* fixed py binding, again
* Update CREDITS.TXT
* fixed formatting and a cast
* Changed param from int to uint8_t, fixed warnings
2018-07-04 22:47:55 +08:00
ed1246d79b
add Ethereum VM architecture
2018-03-31 17:29:22 +08:00
ef4a2dbccc
tests: cleanup
2016-10-17 14:42:32 +08:00
c45f1db564
Merge remote-tracking branch 'upstream/next' into next
2016-05-11 22:52:34 -07:00
45e5eab646
port Windows driver support
2016-05-11 21:48:32 -07:00
cbf5d3d440
Remove never used cs_x86_op::fp
2016-04-23 14:45:24 +03:00
50c352c9d6
Make tests fail loudly
2015-05-31 09:01:38 +02:00
19ee2d10b3
inttypes.h fix
2015-03-29 21:16:38 +08:00
3a99bc6977
tests: fix an warning on big left shifting. issue reported by Coverity
2015-03-27 00:51:47 +08:00
efffe787d1
Add new API and start to provide access information for instruction operands
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- New API cs_regs_access() that provide registers being read & modified by instruction
- New field cs_x86_op.access provides access info (READ, WRITE) for each operand
- New field cs_x86.eflags provides EFLAGS affected by instruction
- Extend cs_detail.{regs_read, regs_write} from uint8_t to uint16_t type
2015-03-25 15:02:13 +08:00
a81bf4247c
x86: add new field @xop_cc to struct @cs_x86
2015-03-07 13:37:32 +08:00
9c10ace558
Make pkg-config and source consistent with installation
2015-02-24 05:03:04 +01:00
ced9d24e35
Workaround missing <inttypes.h> on MSVC 2010
2014-09-21 17:27:11 +02:00
0beb0d494b
api: get back the old API cs_disasm() & mark cs_disasm_ex() deprecated. cs_disasm_ex() will be removed in the future
2014-08-27 22:55:29 +08:00
9be1f93f88
fixed warnings in MSVC x64 compilation
2014-08-26 23:51:12 +08:00
9f6ed7155a
x86: add @rex to cs_x86 struct. updated python & java binding for this change
2014-07-01 10:13:28 +08:00
1a66fecdbc
x86: support avx_sae & avx_rm in cs_x86 struct. this also updates Python & Java bindings following the core's change
2014-06-26 12:09:15 +08:00
92a3d4c079
x86: add AVX's zero_opmask to cs_x86_op struct. updated Python & Java bindings for this change
2014-06-25 23:10:39 +08:00
f1ec52628e
x86: provide size for X86_OP_IMM operand. thank Gabriel Quadros for some suggestions
2014-06-25 22:03:18 +08:00
4c5eabc32b
x86: support SSE_CC & AVX_CC in cs_x86 struct. this also updates Python & Java bindings
2014-06-24 23:50:41 +08:00
0d716450fc
x86: add avx_bcast to cs_x86_op to support AVX512 instructions. this also updates Python & Java binding
2014-06-24 22:51:56 +08:00
bb6440c5ef
x86: extend cs_x86.opcode to 4 bytes to contain EVEX opcode. this also updates Python binding following this interface change
2014-06-24 21:46:54 +08:00
14ba46bfab
x86: add segment to x86_op_mem struct. this fixes a bug in generating detail for instructions with segment override. bug reported by Sean Heelan.
2014-06-24 14:32:01 +08:00
d948dd42b8
tests/test_x86: prefix[] size is now 4, not 5
2014-06-20 13:55:24 +08:00
1085073f8f
x86: remove disp_size, imm_size, op_size. add size to each operand. thanks Gabriel Quadros for some nice ideas
2014-06-18 12:16:24 +08:00
cb2c4f90bf
test_x86: output sib_base, sib_index, sib_scale separately
2014-05-17 13:12:29 +08:00
e47b8121fe
test_x86.c now works on VS2012
2014-05-09 21:03:29 +01:00
5b556e5fcf
tests: C89
2014-04-11 10:15:26 +08:00
54015f45bc
tests: add sanity check on insn->detail, since it can be NULL when SKIPDATA option is ON
2014-04-10 00:02:04 +08:00
226d7dca64
change API cs_close() to take pointer to handle as argument. this lets us invalidate the closed handle
2014-02-27 22:20:39 +08:00
491469155e
tests: continue to next tests rather than quit when failing to initialize a test
2014-02-22 16:54:44 +08:00
ceae16d5a9
tests: report error when cs_open() failure
2014-01-19 16:04:23 +08:00
39b812d9e9
switch detail to be CS_OPT_OFF by default
2014-01-07 23:36:26 +08:00
04c19beefe
rename API cs_disasm_dyn() to cs_disasm_ex(), and intentionally breaks compatibility with 1.0
2013-12-25 13:26:22 +08:00
4fe224b1ed
change API cs_disasm_dyn(): break cs_insn into 2 structures, and put all details into new structure cs_detail. this break API compatibility
2013-12-24 16:49:36 +08:00
bdaf3b5089
x86: delete useless constant values assigned for instructions in x86.h
2013-12-09 00:55:49 +08:00
b4ce38355a
x86: map xstorerng alias instruction back to xstore. bug reported by Nicolas Ruff
2013-12-06 08:06:21 +08:00
641b78375f
x86: fix relative call. bug reported by Joxean Koret
2013-12-04 16:56:40 +08:00
c618db4473
change option names for cs_option(), and update python binding accordingly to support new cs_option()
2013-12-04 00:05:04 +08:00
b8ce68ec05
change cs_option() API to be more flexible with option value
2013-12-03 23:45:08 +08:00
01aba002e3
add cs_option() API. move ATT & Intel syntax here, rather than having them as CS_MODE, which is wrong
2013-12-03 21:00:09 +08:00
6d552e5540
x86: fix bug in relative jump. reported by Joxean
2013-12-03 18:23:53 +08:00
5df9e4be91
tests: change variable address's type to uint64_t
2013-12-03 15:02:12 +08:00
7b7b40c879
tests: now @address is uint64_t, no need to typecast for PRIx64 anymore
2013-12-03 12:24:06 +08:00
d57fa4f68e
x86: added bunch of test insn (commented)
2013-12-03 00:45:39 +08:00
9c950c15d6
x86: fix all the shift rotate insns with 1 as immediate: shl, shr, sar, ror, rol. thus, removed the hack on this insns.
2013-12-02 23:20:07 +08:00
8fcec67893
x86: do not sign-extend immediate. this fixes the issues reported by LongLD
2013-12-02 22:03:30 +08:00
b9b3d29ff5
x86: print segment register in some insns with memory references. This fixes the bug reported by Edgar & Attila
2013-12-02 16:21:55 +08:00
Scott Knight