079d94d7f0
arm: POP {reg} read/write SP register. this fixes #913
2017-05-04 17:21:41 +08:00
e1e2b5b790
fix compiling error in MS VS2015 ( #869 )
...
for issue #868
2017-04-26 09:10:44 +08:00
335b85c627
arm64: fix immediate number in detail mode. see #860
2017-02-26 18:17:39 +08:00
96309544ba
arm: add IMM operand for printPostIdxImm8s4Operand(). issue #861
2017-02-22 09:26:54 +08:00
0f456b3379
switch endian mode with cs_option() for Arm/Arm64/Mips/Sparc. fix issue #849
2017-02-01 11:17:13 +08:00
952d534d1b
Patch for issue #842
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The SETEND instruction is a 16 bit Thumb instruction which is included
in T variants of ARMv6 and above, but is not available in M-Class cores
(see ARM Compiler toolchain Assembler Reference Ver 5.0).
To be consistent with other similar instructions its group flags have
been updated to be:
{ARM_GRP_THUMB, ARM_GRP_V6, ARM_GRP_NOTMCLASS,0}
2017-01-18 17:35:42 +00:00
da38d99d51
Use the correct mapping for 32-bit Thumb Big-Endian insns
2016-11-13 23:18:13 -05:00
a11c9472be
arm: update imm in printOperand() to fix error reported by @trufae in PR #764
2016-09-22 22:25:09 +08:00
c2cdb006fd
arm: treat ARM address as unsigned
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It should be unsigned because:
* It does arithmetic operations
* Format strings have "%u" instead of "%d"
2016-09-03 14:28:46 +09:00
0bb4433f26
arm: fix issue #740
2016-08-11 17:01:48 +08:00
2729f3bb33
fix #681
2016-05-16 08:32:58 -07:00
b158b93a7d
remove myinttypes.h
2016-04-26 09:47:30 +08:00
c7dcf9c9a0
Fix classification of ARM jump instructions
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All jump instructions have been classified based on the direct
and indirect_branch flags instead of explicitly stating ARM_GRP_JUMP.
2015-12-17 12:36:48 +01:00
763ac62498
arm: another fix for #446 . bug reported by @uxmal
2015-08-19 22:36:37 +08:00
8b012d5e7a
arm: fix issue #459 reported by Ahmed Garhy
2015-08-15 14:16:39 +08:00
4fcb31c9d3
Fix Thumb disassembler memory corruption with IT sequence (issue #385 )
2015-06-03 15:38:45 +02:00
ded15775af
arm: fix an warning on conversion from uint64_t to bool. issue reported by @yegord
2015-05-24 21:33:17 +08:00
478595dc3a
arm: remove ASRS, LSRS, SUBS & MOVS from mapping table insns[]. backported from the 'next' branch, but do not really remove these 'dead' instructions for compatibility reason
2015-05-08 15:08:35 +08:00
5dba2c3742
arm: BLX should read PC & modify LR registers. bug reported by Zach Riggle
2015-05-08 15:04:09 +08:00
9d60607645
inttypes.h fix
2015-03-29 18:29:06 +08:00
726ade0c8d
arm: more optimization on MCInstrDesc struct to reduce the library size by further 20KB
2015-03-10 17:30:26 +08:00
e220b503f1
arm: rever the change on OperandInfo* in the last commit
2015-03-10 16:45:15 +08:00
3d00666e90
optimize MCInstrDesc to reduce its size
2015-03-10 15:40:09 +08:00
c141af9052
Silencing Clang warning bys casting values
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Warnings were: "Implicit conversion loses integer precision: 'size_t' to 'cs_mode'/'cs_opt_value'"
2015-03-02 22:11:55 -05:00
8c9fd12bc3
arm: fix some warnings reported by MSVC
2015-02-25 18:01:02 +08:00
996f06c30f
Correct printAM3PreOrOffsetIndexOp disp value
2015-02-15 18:22:51 +09:00
61cbeabb44
Remove incorrect ITBlock.size = 0
2015-02-15 01:40:58 +09:00
9426ad572f
arm: add few more post-indexed instructions doing writeback
2015-01-21 20:03:40 +08:00
7bbb4336a8
arm: fix a bug in the last commit
2015-01-21 20:03:29 +08:00
e19490e8f7
arm: some load/store instructions writeback without bang letter. bug reported by @jabba2989
2015-01-21 20:03:21 +08:00
f2157deacc
arm: in Thumb mode, ADC & SBC do not update flags. bug reported by @jabba2989
2015-01-13 22:18:05 +08:00
07526e989b
arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP.
2014-12-30 10:47:04 +08:00
db684b2398
arm: BL & BLX do not read SP, but PC register. issue reported by Der Rek
2014-12-27 16:26:42 +08:00
3caf837c9a
arm: alias LDR instruction with operands '[sp], 4' to POP. suggested by Pancake
2014-11-27 14:34:40 +08:00
a2934a7b6a
arm: print immediate op of MVN instruction in positive hexadecimal form. issue reported by Pancake
2014-11-25 21:02:18 +08:00
c00bc2efb6
fix the left-over C89 issues introduced by Pedro
2014-11-21 19:29:47 +08:00
68197d9a5e
Make it C89 compatible.
2014-11-20 13:45:43 +00:00
202da41980
Fix compiler warnings about different sizes and sign.
2014-11-20 12:13:19 +00:00
1ffc1b2201
arm: fix printMemBOption() that was wrongly fixed in 51888c3e08
2014-11-12 13:33:15 +08:00
51888c3e08
arm: fix some bugs reported by VS2010. thanks Axel for testing
2014-11-11 23:59:23 +08:00
8cdafda551
arm: add new field mem_barrier to cs_arm struct. this requires changes in bindings
2014-11-11 22:30:30 +08:00
278e7270d9
arm: print immediate in positive form for AND/ORR/EOR/BIC instructions
2014-11-11 12:50:43 +08:00
2ac5d79353
arm: print floating point number in %e format
2014-11-10 21:46:34 +08:00
6acaaa5e44
arm: printAddrMode5Operand() is wrong on calculating subtracted variable
2014-11-10 17:41:05 +08:00
4e17eefc57
arm: lowercase for apsr_nzcv
2014-11-10 17:02:32 +08:00
d865f39a68
arm: use lowercase for special registers
2014-11-10 16:38:17 +08:00
2593e22932
arm: support V8 as a mode for A32 encodings
2014-11-10 16:35:38 +08:00
c2ea812ea7
fix cs_group_name() after the change on generic group ids
2014-10-31 15:36:19 +08:00
c58e704517
do not need to explicitly assign values for operand types in the last commit
2014-10-31 13:55:18 +08:00
21ac056728
use common operand types across all architectures. this adds cs_op_type to capstone.h. suggestion by @zneak
2014-10-31 13:08:28 +08:00
