Virtualization
/
capstone
mirror of https://gitlab.com/qemu-project/capstone.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,026 Commits 18 Branches 46 Tags 73 MiB
Commit Graph

4026 Commits

Author SHA1 Message Date
Nguyen Anh Quynh cafce5dc89 Merge branch 'master' into next 2018-12-19 07:49:32 +07:00
Nguyen Anh Quynh 863044dc31 remove rc1 from pkgconfig.mk 2018-12-19 07:49:02 +07:00
Nguyen Anh Quynh 75c05281b4 Merge branch 'master' of github.com:aquynh/capstone 2018-12-19 00:31:46 +08:00
Nguyen Anh Quynh 55386e7ba4 RELEASE_NOTES 2018-12-19 00:31:23 +08:00
Ammar bae63f65c1 x86: correct access mode for cmp instruction (#1309) 
cmp instruction does not modify its operands. Currently, cmp
variants that accept a memory operand have CS_AC_WRITE access mode
set. This commit removes CS_AC_WRITE mode from cmp variants that
have it.
 2018-12-18 23:22:30 +08:00
Nguyen Anh Quynh 856ef5892c MOS65XX: lowercase for MOS65XX_AM_ACC 2018-12-18 22:46:23 +08:00
Nguyen Anh Quynh e835bdbd89 Merge branch 'master' into next 2018-12-18 22:44:57 +08:00
Nguyen Anh Quynh cc8da331d3 M680X: lowercase for registers & FCB instruction 2018-12-18 22:44:12 +08:00
Nguyen Anh Quynh 290828fc31 TMS320C64x: lowercase for instruction mnemonics, registers & group names 2018-12-18 22:40:31 +08:00
Nguyen Anh Quynh 31b7acde26 M680X: lowercase for instruction mnemonics & group names 2018-12-18 22:33:00 +08:00
Nguyen Anh Quynh 1d96deec98 MOS65XX: lowercase for instruction mnemonic 2018-12-18 22:28:33 +08:00
Nguyen Anh Quynh a0cdd0bfbe ChangeLog for v4.0 2018-12-18 22:25:39 +08:00
Catena cyber b8c20f47a8 MOS65XX fuzzing (#1307) 2018-12-18 09:24:10 +08:00
Nguyen Anh Quynh 57d9bda493 fix ChangeLog 2018-12-17 19:10:31 +08:00
Nguyen Anh Quynh 9433fc1061 Merge branch 'master' of https://github.com/aquynh/capstone 2018-12-17 14:04:21 +08:00
Nguyen Anh Quynh 1781e589f2 HACK.TXT: add TMS320C64x 2018-12-16 21:54:29 +08:00
Nguyen Anh Quynh 921dbb2d3a HACK.TXT: add TMS320C64x 2018-12-16 21:53:56 +08:00
mephi42 d9b8079aba Update SystemZ to LLVM commit 5ad902a6 (#1306) 2018-12-16 21:48:51 +08:00
Nguyen Anh Quynh e6ceee576d mos65xx: fix warnings reported by CI 2018-12-16 20:47:52 +08:00
Nguyen Anh Quynh 5c634289b4 bump version to 4.1 2018-12-16 20:18:20 +08:00
Nguyen Anh Quynh 6318f623f1 tests: add MOS65XX sample to test_basic.c 2018-12-16 20:14:07 +08:00
Nguyen Anh Quynh 3933674e62 mos65xx: solve conflicts 2018-12-16 20:09:28 +08:00
Nguyen Anh Quynh efaee7ae44 Merge branch 'master' into next 2018-12-16 19:58:43 +08:00
Nguyen Anh Quynh 7732f3a354 update HACK.TXT 2018-12-12 16:30:45 +07:00
Catena cyber 3a0467cfea Use whole corpus for regression testing (#1302) 
* Use whole corpus for regression testing

* differetial fuzzing against llvm-mc

* Download corpus from another repo
 2018-12-11 09:33:31 +07:00
Nguyen Anh Quynh 3a6a8d59d6 fix conflicts 2018-12-08 09:52:08 +07:00
Sebastian Macke 8663d75c56 MOS65XX: Add binding for python 
Signed-off-by: Sebastian Macke <sebastian@macke.de>
 2018-12-06 22:53:43 +01:00
Sebastian Macke 7436f54447 MOS65XX: Add architecture to main readme and add name to contributors 
Signed-off-by: Sebastian Macke <sebastian@macke.de>
 2018-12-06 22:53:43 +01:00
Sebastian Macke 87221fa742 Add support for the MOS65XX family such as the MOS 6502. 
Signed-off-by: Sebastian Macke <sebastian@macke.de>
 2018-12-06 22:53:33 +01:00
Catena cyber a69f7880a8 Continuous integration for fuzzing (#1297) 
* Continuous integration for fuzzing

* Simplify fuzz testing output

* Makefile for suite fuzz

* fixup

* Code review taken into acount

* More readable fuzz harness

Inputs specify only on first line the mode
 2018-12-04 15:02:16 +07:00
keenk 37c99df87c Fix a few registry access mode mappings (#1295) 2018-11-26 14:05:29 +07:00
Nguyen Anh Quynh 4948fd1b56 PPC: print 16bit imm as unsigned 2018-11-25 21:12:05 +07:00
Nguyen Anh Quynh f5960097e2
Update README.md 
add D binding
 2018-11-21 17:45:33 +08:00
Nguyen Anh Quynh 398a047dfc add D binding to README 2018-11-21 17:44:33 +08:00
Dimitri Bohlender 1d18225453 Update README (#1291) 2018-11-21 17:43:15 +08:00
amirgon 29893c63e3 Recognize MSYS compiler as MINGW compiler (#1290) 2018-11-21 00:46:12 +08:00
Dimitri Bohlender f01c267f88 Typo in register's name (#1282) 
Fixed Minor typo, i.e. the friendly string representation of X86_REG_ST0 was "st(0"
 2018-11-02 07:43:54 +08:00
Nguyen Anh Quynh 641a0dd95b x86: fix instruction suffix of MOV to segment register for ATT syntax. issue #1240 2018-10-26 14:08:18 +08:00
Nguyen Anh Quynh 88d0442e9f x86: fix operand access of FSTP (#1255) 2018-10-25 23:22:48 +08:00
Derrick McKee c3bc43e354 Generate capstone.pc to the location it is installed from (#1265) 
* forcing capstone.pc to be generated in the same place it is installed from

* x86: fix operand access of SETE & SETNE (#1262)

* forcing capstone.pc to be generated in the same place it is installed from
 2018-10-23 19:42:36 -03:00
ael 0a39b785d3 fix include path in pkg-config template (#1276) 2018-10-23 19:42:01 -03:00
Nguyen Anh Quynh 9408c0de4f Merge branch 'master' of github.com:aquynh/capstone 2018-10-10 14:14:48 +08:00
Nguyen Anh Quynh 260fbdc313 x86: fix operand access of SETE & SETNE (#1262) 2018-10-10 14:07:07 +08:00
blacktop 0999ad1b5e Remove i386 from Makefile (#1260) 2018-10-03 15:21:54 +08:00
Nguyen Anh Quynh a6b87b7bc3 x86: fix operand access of fistp & fstp, in #1255 2018-10-02 12:22:13 +02:00
Nguyen Anh Quynh fc8ba23378 x86: fix operand access of CMP in #1253 2018-10-02 12:18:29 +02:00
Hugo fbeffa489c Add python_requires and update Trove classifiers (#1251) 2018-10-02 17:45:45 +08:00
keenk d872bcdcce Add files via upload (#1256) 
Correct register access flag for the movdqa instruction
 2018-10-02 17:45:11 +08:00
Bruce Mitchener aed8bffd61 Fix typo: combined. (#1254) 2018-10-02 17:44:39 +08:00
Nguyen Anh Quynh 2b4aec9c76 bindings: make bindings/const_generator.py compatible with recent reformat of C headers 2018-10-01 20:29:39 +08:00