987 lines
23 KiB
C
987 lines
23 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the AArch64 target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
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#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
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// FIXME: Is it easiest to fix this layering violation by moving the .inc
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// #includes from AArch64MCTargetDesc.h to here?
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#include <capstone/platform.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "../../MCInstPrinter.h"
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#include "../../utils.h"
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#include "capstone/aarch64.h"
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#define GET_SUBTARGETINFO_ENUM
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#include "AArch64GenSubtargetInfo.inc"
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#define GET_REGINFO_ENUM
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#define GET_REGINFO_MC_DESC
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#include "AArch64GenRegisterInfo.inc"
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#define GET_INSTRINFO_ENUM
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#include "AArch64GenInstrInfo.inc"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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static inline unsigned getWRegFromXReg(unsigned Reg)
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{
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switch (Reg) {
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case AArch64_X0:
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return AArch64_W0;
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case AArch64_X1:
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return AArch64_W1;
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case AArch64_X2:
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return AArch64_W2;
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case AArch64_X3:
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return AArch64_W3;
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case AArch64_X4:
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return AArch64_W4;
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case AArch64_X5:
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return AArch64_W5;
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case AArch64_X6:
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return AArch64_W6;
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case AArch64_X7:
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return AArch64_W7;
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case AArch64_X8:
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return AArch64_W8;
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case AArch64_X9:
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return AArch64_W9;
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case AArch64_X10:
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return AArch64_W10;
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case AArch64_X11:
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return AArch64_W11;
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case AArch64_X12:
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return AArch64_W12;
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case AArch64_X13:
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return AArch64_W13;
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case AArch64_X14:
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return AArch64_W14;
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case AArch64_X15:
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return AArch64_W15;
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case AArch64_X16:
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return AArch64_W16;
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case AArch64_X17:
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return AArch64_W17;
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case AArch64_X18:
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return AArch64_W18;
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case AArch64_X19:
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return AArch64_W19;
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case AArch64_X20:
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return AArch64_W20;
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case AArch64_X21:
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return AArch64_W21;
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case AArch64_X22:
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return AArch64_W22;
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case AArch64_X23:
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return AArch64_W23;
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case AArch64_X24:
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return AArch64_W24;
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case AArch64_X25:
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return AArch64_W25;
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case AArch64_X26:
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return AArch64_W26;
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case AArch64_X27:
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return AArch64_W27;
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case AArch64_X28:
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return AArch64_W28;
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case AArch64_FP:
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return AArch64_W29;
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case AArch64_LR:
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return AArch64_W30;
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case AArch64_SP:
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return AArch64_WSP;
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case AArch64_XZR:
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return AArch64_WZR;
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}
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// For anything else, return it unchanged.
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return Reg;
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}
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static inline unsigned getXRegFromWReg(unsigned Reg)
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{
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switch (Reg) {
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case AArch64_W0:
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return AArch64_X0;
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case AArch64_W1:
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return AArch64_X1;
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case AArch64_W2:
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return AArch64_X2;
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case AArch64_W3:
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return AArch64_X3;
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case AArch64_W4:
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return AArch64_X4;
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case AArch64_W5:
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return AArch64_X5;
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case AArch64_W6:
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return AArch64_X6;
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case AArch64_W7:
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return AArch64_X7;
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case AArch64_W8:
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return AArch64_X8;
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case AArch64_W9:
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return AArch64_X9;
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case AArch64_W10:
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return AArch64_X10;
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case AArch64_W11:
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return AArch64_X11;
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case AArch64_W12:
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return AArch64_X12;
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case AArch64_W13:
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return AArch64_X13;
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case AArch64_W14:
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return AArch64_X14;
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case AArch64_W15:
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return AArch64_X15;
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case AArch64_W16:
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return AArch64_X16;
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case AArch64_W17:
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return AArch64_X17;
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case AArch64_W18:
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return AArch64_X18;
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case AArch64_W19:
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return AArch64_X19;
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case AArch64_W20:
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return AArch64_X20;
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case AArch64_W21:
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return AArch64_X21;
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case AArch64_W22:
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return AArch64_X22;
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case AArch64_W23:
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return AArch64_X23;
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case AArch64_W24:
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return AArch64_X24;
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case AArch64_W25:
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return AArch64_X25;
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case AArch64_W26:
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return AArch64_X26;
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case AArch64_W27:
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return AArch64_X27;
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case AArch64_W28:
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return AArch64_X28;
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case AArch64_W29:
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return AArch64_FP;
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case AArch64_W30:
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return AArch64_LR;
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case AArch64_WSP:
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return AArch64_SP;
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case AArch64_WZR:
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return AArch64_XZR;
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}
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// For anything else, return it unchanged.
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return Reg;
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}
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static inline unsigned getXRegFromXRegTuple(unsigned RegTuple)
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{
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switch (RegTuple) {
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case AArch64_X0_X1_X2_X3_X4_X5_X6_X7:
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return AArch64_X0;
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case AArch64_X2_X3_X4_X5_X6_X7_X8_X9:
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return AArch64_X2;
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case AArch64_X4_X5_X6_X7_X8_X9_X10_X11:
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return AArch64_X4;
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case AArch64_X6_X7_X8_X9_X10_X11_X12_X13:
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return AArch64_X6;
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case AArch64_X8_X9_X10_X11_X12_X13_X14_X15:
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return AArch64_X8;
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case AArch64_X10_X11_X12_X13_X14_X15_X16_X17:
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return AArch64_X10;
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case AArch64_X12_X13_X14_X15_X16_X17_X18_X19:
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return AArch64_X12;
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case AArch64_X14_X15_X16_X17_X18_X19_X20_X21:
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return AArch64_X14;
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case AArch64_X16_X17_X18_X19_X20_X21_X22_X23:
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return AArch64_X16;
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case AArch64_X18_X19_X20_X21_X22_X23_X24_X25:
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return AArch64_X18;
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case AArch64_X20_X21_X22_X23_X24_X25_X26_X27:
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return AArch64_X20;
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case AArch64_X22_X23_X24_X25_X26_X27_X28_FP:
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return AArch64_X22;
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}
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// For anything else, return it unchanged.
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return RegTuple;
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}
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static inline unsigned getBRegFromDReg(unsigned Reg)
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{
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switch (Reg) {
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case AArch64_D0:
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return AArch64_B0;
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case AArch64_D1:
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return AArch64_B1;
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case AArch64_D2:
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return AArch64_B2;
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case AArch64_D3:
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return AArch64_B3;
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case AArch64_D4:
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return AArch64_B4;
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case AArch64_D5:
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return AArch64_B5;
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case AArch64_D6:
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return AArch64_B6;
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case AArch64_D7:
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return AArch64_B7;
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case AArch64_D8:
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return AArch64_B8;
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case AArch64_D9:
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return AArch64_B9;
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case AArch64_D10:
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return AArch64_B10;
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case AArch64_D11:
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return AArch64_B11;
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case AArch64_D12:
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return AArch64_B12;
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case AArch64_D13:
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return AArch64_B13;
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case AArch64_D14:
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return AArch64_B14;
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case AArch64_D15:
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return AArch64_B15;
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case AArch64_D16:
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return AArch64_B16;
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case AArch64_D17:
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return AArch64_B17;
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case AArch64_D18:
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return AArch64_B18;
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case AArch64_D19:
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return AArch64_B19;
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case AArch64_D20:
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return AArch64_B20;
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case AArch64_D21:
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return AArch64_B21;
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case AArch64_D22:
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return AArch64_B22;
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case AArch64_D23:
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return AArch64_B23;
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case AArch64_D24:
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return AArch64_B24;
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case AArch64_D25:
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return AArch64_B25;
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case AArch64_D26:
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return AArch64_B26;
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case AArch64_D27:
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return AArch64_B27;
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case AArch64_D28:
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return AArch64_B28;
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case AArch64_D29:
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return AArch64_B29;
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case AArch64_D30:
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return AArch64_B30;
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case AArch64_D31:
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return AArch64_B31;
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}
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// For anything else, return it unchanged.
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return Reg;
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}
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static inline unsigned getDRegFromBReg(unsigned Reg)
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{
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switch (Reg) {
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case AArch64_B0:
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return AArch64_D0;
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case AArch64_B1:
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return AArch64_D1;
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case AArch64_B2:
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return AArch64_D2;
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case AArch64_B3:
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return AArch64_D3;
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case AArch64_B4:
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return AArch64_D4;
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case AArch64_B5:
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return AArch64_D5;
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case AArch64_B6:
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return AArch64_D6;
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case AArch64_B7:
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return AArch64_D7;
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case AArch64_B8:
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return AArch64_D8;
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case AArch64_B9:
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return AArch64_D9;
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case AArch64_B10:
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return AArch64_D10;
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case AArch64_B11:
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return AArch64_D11;
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case AArch64_B12:
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return AArch64_D12;
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case AArch64_B13:
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return AArch64_D13;
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case AArch64_B14:
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return AArch64_D14;
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case AArch64_B15:
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return AArch64_D15;
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case AArch64_B16:
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return AArch64_D16;
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case AArch64_B17:
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return AArch64_D17;
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case AArch64_B18:
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return AArch64_D18;
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case AArch64_B19:
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return AArch64_D19;
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case AArch64_B20:
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return AArch64_D20;
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case AArch64_B21:
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return AArch64_D21;
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case AArch64_B22:
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return AArch64_D22;
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case AArch64_B23:
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return AArch64_D23;
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case AArch64_B24:
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return AArch64_D24;
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case AArch64_B25:
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return AArch64_D25;
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case AArch64_B26:
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return AArch64_D26;
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case AArch64_B27:
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return AArch64_D27;
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case AArch64_B28:
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return AArch64_D28;
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case AArch64_B29:
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return AArch64_D29;
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case AArch64_B30:
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return AArch64_D30;
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case AArch64_B31:
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return AArch64_D31;
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}
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// For anything else, return it unchanged.
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return Reg;
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}
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static inline bool atomicBarrierDroppedOnZero(unsigned Opcode)
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{
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switch (Opcode) {
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case AArch64_LDADDAB:
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case AArch64_LDADDAH:
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case AArch64_LDADDAW:
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case AArch64_LDADDAX:
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case AArch64_LDADDALB:
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case AArch64_LDADDALH:
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case AArch64_LDADDALW:
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case AArch64_LDADDALX:
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case AArch64_LDCLRAB:
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case AArch64_LDCLRAH:
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case AArch64_LDCLRAW:
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case AArch64_LDCLRAX:
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case AArch64_LDCLRALB:
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case AArch64_LDCLRALH:
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case AArch64_LDCLRALW:
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case AArch64_LDCLRALX:
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case AArch64_LDEORAB:
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case AArch64_LDEORAH:
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case AArch64_LDEORAW:
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case AArch64_LDEORAX:
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case AArch64_LDEORALB:
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case AArch64_LDEORALH:
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case AArch64_LDEORALW:
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case AArch64_LDEORALX:
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case AArch64_LDSETAB:
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case AArch64_LDSETAH:
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case AArch64_LDSETAW:
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case AArch64_LDSETAX:
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case AArch64_LDSETALB:
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case AArch64_LDSETALH:
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case AArch64_LDSETALW:
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case AArch64_LDSETALX:
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case AArch64_LDSMAXAB:
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case AArch64_LDSMAXAH:
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case AArch64_LDSMAXAW:
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case AArch64_LDSMAXAX:
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case AArch64_LDSMAXALB:
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case AArch64_LDSMAXALH:
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case AArch64_LDSMAXALW:
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case AArch64_LDSMAXALX:
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case AArch64_LDSMINAB:
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case AArch64_LDSMINAH:
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case AArch64_LDSMINAW:
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case AArch64_LDSMINAX:
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case AArch64_LDSMINALB:
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case AArch64_LDSMINALH:
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case AArch64_LDSMINALW:
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case AArch64_LDSMINALX:
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case AArch64_LDUMAXAB:
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case AArch64_LDUMAXAH:
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case AArch64_LDUMAXAW:
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case AArch64_LDUMAXAX:
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case AArch64_LDUMAXALB:
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case AArch64_LDUMAXALH:
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case AArch64_LDUMAXALW:
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case AArch64_LDUMAXALX:
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case AArch64_LDUMINAB:
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case AArch64_LDUMINAH:
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case AArch64_LDUMINAW:
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case AArch64_LDUMINAX:
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case AArch64_LDUMINALB:
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case AArch64_LDUMINALH:
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case AArch64_LDUMINALW:
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case AArch64_LDUMINALX:
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case AArch64_SWPAB:
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case AArch64_SWPAH:
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case AArch64_SWPAW:
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case AArch64_SWPAX:
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case AArch64_SWPALB:
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case AArch64_SWPALH:
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case AArch64_SWPALW:
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case AArch64_SWPALX:
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return true;
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}
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return false;
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}
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// MOVE-NOTICE: AArch64CC_CondCode : moved to aarch64.h
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// MOVE-NOTICE: AArch64CC_getCondCodeName : moved to aarch64.h
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// MOVE-NOTICE: AArch64CC_getInvertedCondCode : moved to aarch64.h
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// MOVE-NOTICE: AArch64CC_getNZCVToSatisfyCondCode : moved to aarch64.h
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typedef struct SysAlias {
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const char *Name;
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aarch64_sysop_alias SysAlias;
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uint16_t Encoding;
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aarch64_insn_group FeaturesRequired[3];
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} SysAlias;
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typedef struct SysAliasReg {
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const char *Name;
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aarch64_sysop_reg SysReg;
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uint16_t Encoding;
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bool NeedsReg;
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aarch64_insn_group FeaturesRequired[3];
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} SysAliasReg;
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typedef struct SysAliasImm {
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const char *Name;
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aarch64_sysop_imm SysImm;
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uint16_t ImmValue;
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uint16_t Encoding;
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aarch64_insn_group FeaturesRequired[3];
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} SysAliasImm;
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// CS namespace begin: AArch64SVCR
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|
|
#define AArch64SVCR_SVCR SysAlias
|
|
|
|
#define GET_SVCR_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64SVCR
|
|
|
|
// CS namespace begin: AArch64AT
|
|
|
|
#define AArch64AT_AT SysAlias
|
|
|
|
#define GET_AT_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64AT
|
|
|
|
// CS namespace begin: AArch64DB
|
|
|
|
#define AArch64DB_DB SysAlias
|
|
|
|
#define GET_DB_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64DB
|
|
|
|
// CS namespace begin: AArch64DBnXS
|
|
|
|
#define AArch64DBnXS_DBnXS SysAliasImm
|
|
|
|
#define GET_DBNXS_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64DBnXS
|
|
|
|
// CS namespace begin: AArch64DC
|
|
|
|
#define AArch64DC_DC SysAlias
|
|
|
|
#define GET_DC_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64DC
|
|
|
|
// CS namespace begin: AArch64IC
|
|
|
|
#define AArch64IC_IC SysAliasReg
|
|
|
|
#define GET_IC_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64IC
|
|
|
|
// CS namespace begin: AArch64ISB
|
|
|
|
#define AArch64ISB_ISB SysAlias
|
|
|
|
#define GET_ISB_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64ISB
|
|
|
|
// CS namespace begin: AArch64TSB
|
|
|
|
#define AArch64TSB_TSB SysAlias
|
|
|
|
#define GET_TSB_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64TSB
|
|
|
|
// CS namespace begin: AArch64PRFM
|
|
|
|
#define AArch64PRFM_PRFM SysAlias
|
|
|
|
#define GET_PRFM_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64PRFM
|
|
|
|
// CS namespace begin: AArch64SVEPRFM
|
|
|
|
#define AArch64SVEPRFM_SVEPRFM SysAlias
|
|
|
|
#define GET_SVEPRFM_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64SVEPRFM
|
|
|
|
// CS namespace begin: AArch64RPRFM
|
|
|
|
#define AArch64RPRFM_RPRFM SysAlias
|
|
|
|
#define GET_RPRFM_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64RPRFM
|
|
|
|
// CS namespace begin: AArch64SVEPredPattern
|
|
|
|
typedef struct SVEPREDPAT {
|
|
const char *Name;
|
|
aarch64_sysop_alias SysAlias;
|
|
uint16_t Encoding;
|
|
} AArch64SVEPredPattern_SVEPREDPAT;
|
|
|
|
#define GET_SVEPREDPAT_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64SVEPredPattern
|
|
|
|
// CS namespace begin: AArch64SVEVecLenSpecifier
|
|
|
|
typedef struct SVEVECLENSPECIFIER {
|
|
const char *Name;
|
|
aarch64_sysop_alias SysAlias;
|
|
uint16_t Encoding;
|
|
} AArch64SVEVecLenSpecifier_SVEVECLENSPECIFIER;
|
|
|
|
#define GET_SVEVECLENSPECIFIER_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64SVEVecLenSpecifier
|
|
|
|
// namespace AArch64SVEVecLenSpecifier
|
|
|
|
/// Return the number of active elements for VL1 to VL256 predicate pattern,
|
|
/// zero for all other patterns.
|
|
static inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
|
|
{
|
|
switch (Pattern) {
|
|
default:
|
|
return 0;
|
|
case AARCH64_SVEPREDPAT_VL1:
|
|
case AARCH64_SVEPREDPAT_VL2:
|
|
case AARCH64_SVEPREDPAT_VL3:
|
|
case AARCH64_SVEPREDPAT_VL4:
|
|
case AARCH64_SVEPREDPAT_VL5:
|
|
case AARCH64_SVEPREDPAT_VL6:
|
|
case AARCH64_SVEPREDPAT_VL7:
|
|
case AARCH64_SVEPREDPAT_VL8:
|
|
return Pattern;
|
|
case AARCH64_SVEPREDPAT_VL16:
|
|
return 16;
|
|
case AARCH64_SVEPREDPAT_VL32:
|
|
return 32;
|
|
case AARCH64_SVEPREDPAT_VL64:
|
|
return 64;
|
|
case AARCH64_SVEPREDPAT_VL128:
|
|
return 128;
|
|
case AARCH64_SVEPREDPAT_VL256:
|
|
return 256;
|
|
}
|
|
}
|
|
|
|
/// Return specific VL predicate pattern based on the number of elements.
|
|
static inline unsigned getSVEPredPatternFromNumElements(unsigned MinNumElts)
|
|
{
|
|
switch (MinNumElts) {
|
|
default:
|
|
return 0;
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
case 7:
|
|
case 8:
|
|
return MinNumElts;
|
|
case 16:
|
|
return AARCH64_SVEPREDPAT_VL16;
|
|
case 32:
|
|
return AARCH64_SVEPREDPAT_VL32;
|
|
case 64:
|
|
return AARCH64_SVEPREDPAT_VL64;
|
|
case 128:
|
|
return AARCH64_SVEPREDPAT_VL128;
|
|
case 256:
|
|
return AARCH64_SVEPREDPAT_VL256;
|
|
}
|
|
}
|
|
|
|
// CS namespace begin: AArch64ExactFPImm
|
|
|
|
typedef struct ExactFPImm {
|
|
const char *Name;
|
|
aarch64_sysop_imm SysImm;
|
|
int Enum;
|
|
const char *Repr;
|
|
} AArch64ExactFPImm_ExactFPImm;
|
|
|
|
enum {
|
|
AArch64ExactFPImm_half = 1,
|
|
AArch64ExactFPImm_one = 2,
|
|
AArch64ExactFPImm_two = 3,
|
|
AArch64ExactFPImm_zero = 0,
|
|
};
|
|
|
|
#define GET_EXACTFPIMM_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64ExactFPImm
|
|
|
|
// CS namespace begin: AArch64PState
|
|
|
|
#define AArch64PState_PStateImm0_15 SysAlias
|
|
|
|
#define GET_PSTATEIMM0_15_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
#define AArch64PState_PStateImm0_1 SysAlias
|
|
|
|
#define GET_PSTATEIMM0_1_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64PState
|
|
|
|
// CS namespace begin: AArch64PSBHint
|
|
|
|
#define AArch64PSBHint_PSB SysAlias
|
|
|
|
#define GET_PSB_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64PSBHint
|
|
|
|
// CS namespace begin: AArch64BTIHint
|
|
|
|
#define AArch64BTIHint_BTI SysAlias
|
|
|
|
#define GET_BTI_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64BTIHint
|
|
|
|
// CS namespace begin: AArch64SE
|
|
|
|
typedef enum ShiftExtSpecifiers {
|
|
AArch64SE_Invalid = -1,
|
|
AArch64SE_LSL,
|
|
AArch64SE_MSL,
|
|
AArch64SE_LSR,
|
|
AArch64SE_ASR,
|
|
AArch64SE_ROR,
|
|
|
|
AArch64SE_UXTB,
|
|
AArch64SE_UXTH,
|
|
AArch64SE_UXTW,
|
|
AArch64SE_UXTX,
|
|
|
|
AArch64SE_SXTB,
|
|
AArch64SE_SXTH,
|
|
AArch64SE_SXTW,
|
|
AArch64SE_SXTX
|
|
} AArch64SE_ShiftExtSpecifiers;
|
|
|
|
// CS namespace end: AArch64SE
|
|
|
|
// CS namespace begin: AArch64Layout
|
|
|
|
// MOVE_NOTICE: AArch64Layout_VectorLayout - move to aarch64.h
|
|
// MOVE_NOTICE: AArch64VectorLayoutToString - move to aarch64.h
|
|
// MOVE_NOTICE: AArch64StringToVectorLayout - move to aarch64.h
|
|
|
|
// CS namespace end: AArch64Layout
|
|
|
|
// CS namespace begin: AArch64SysReg
|
|
|
|
typedef struct SysReg {
|
|
const char *Name;
|
|
aarch64_sysop_reg SysReg;
|
|
const char *AltName;
|
|
aarch64_sysop_reg AliasReg;
|
|
unsigned Encoding;
|
|
bool Readable;
|
|
bool Writeable;
|
|
aarch64_insn_group FeaturesRequired[3];
|
|
} AArch64SysReg_SysReg;
|
|
|
|
#define GET_SYSREG_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
const AArch64SysReg_SysReg *AArch64SysReg_lookupSysRegByName(const char *Name);
|
|
const AArch64SysReg_SysReg *
|
|
AArch64SysReg_lookupSysRegByEncoding(uint16_t Encoding);
|
|
#define AARCH64_GRS_LEN 128
|
|
void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
|
|
|
|
// CS namespace end: AArch64SysReg
|
|
|
|
// CS namespace begin: AArch64TLBI
|
|
|
|
#define AArch64TLBI_TLBI SysAliasReg
|
|
|
|
#define GET_TLBITable_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64TLBI
|
|
|
|
// CS namespace begin: AArch64PRCTX
|
|
|
|
#define AArch64PRCTX_PRCTX SysAliasReg
|
|
|
|
#define GET_PRCTX_DECL
|
|
|
|
#include "AArch64GenSystemOperands.inc"
|
|
|
|
// CS namespace end: AArch64PRCTX
|
|
|
|
// CS namespace begin: AArch64II
|
|
|
|
/// Target Operand Flag enum.
|
|
typedef enum TOF {
|
|
//===------------------------------------------------------------------===//
|
|
// AArch64 Specific MachineOperand flags.
|
|
|
|
AArch64II_MO_NO_FLAG,
|
|
|
|
AArch64II_MO_FRAGMENT = 0x7,
|
|
|
|
/// MO_PAGE - A symbol operand with this flag represents the pc-relative
|
|
/// offset of the 4K page containing the symbol. This is used with the
|
|
/// ADRP instruction.
|
|
AArch64II_MO_PAGE = 1,
|
|
|
|
/// MO_PAGEOFF - A symbol operand with this flag represents the offset of
|
|
/// that symbol within a 4K page. This offset is added to the page address
|
|
/// to produce the complete address.
|
|
AArch64II_MO_PAGEOFF = 2,
|
|
|
|
/// MO_G3 - A symbol operand with this flag (granule 3) represents the high
|
|
/// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
|
|
AArch64II_MO_G3 = 3,
|
|
|
|
/// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
|
|
/// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
|
|
AArch64II_MO_G2 = 4,
|
|
|
|
/// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
|
|
/// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
|
|
AArch64II_MO_G1 = 5,
|
|
|
|
/// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
|
|
/// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
|
|
AArch64II_MO_G0 = 6,
|
|
|
|
/// MO_HI12 - This flag indicates that a symbol operand represents the bits
|
|
/// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
|
|
/// by-12-bits instruction.
|
|
AArch64II_MO_HI12 = 7,
|
|
|
|
/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
|
|
/// reference is actually to the ".refptr.FOO" symbol. This is used for
|
|
/// stub symbols on windows.
|
|
AArch64II_MO_COFFSTUB = 0x8,
|
|
|
|
/// MO_GOT - This flag indicates that a symbol operand represents the
|
|
/// address of the GOT entry for the symbol, rather than the address of
|
|
/// the symbol itself.
|
|
AArch64II_MO_GOT = 0x10,
|
|
|
|
/// MO_NC - Indicates whether the linker is expected to check the symbol
|
|
/// reference for overflow. For example in an ADRP/ADD pair of relocations
|
|
/// the ADRP usually does check, but not the ADD.
|
|
AArch64II_MO_NC = 0x20,
|
|
|
|
/// MO_TLS - Indicates that the operand being accessed is some kind of
|
|
/// thread-local symbol. On Darwin, only one type of thread-local access
|
|
/// exists (pre linker-relaxation), but on ELF the TLSModel used for the
|
|
/// referee will affect interpretation.
|
|
AArch64II_MO_TLS = 0x40,
|
|
|
|
/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
|
|
/// to the symbol is for an import stub. This is used for DLL import
|
|
/// storage class indication on Windows.
|
|
AArch64II_MO_DLLIMPORT = 0x80,
|
|
|
|
/// MO_S - Indicates that the bits of the symbol operand represented by
|
|
/// MO_G0 etc are signed.
|
|
AArch64II_MO_S = 0x100,
|
|
|
|
/// MO_PREL - Indicates that the bits of the symbol operand represented by
|
|
/// MO_G0 etc are PC relative.
|
|
AArch64II_MO_PREL = 0x200,
|
|
|
|
/// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
|
|
/// in bits 56-63.
|
|
/// On a FrameIndex operand, indicates that the underlying memory is tagged
|
|
/// with an unknown tag value (MTE); this needs to be lowered either to an
|
|
/// SP-relative load or store instruction (which do not check tags), or to
|
|
/// an LDG instruction to obtain the tag value.
|
|
AArch64II_MO_TAGGED = 0x400,
|
|
|
|
/// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version
|
|
/// of a symbol, not the original. For dllimport symbols, this means it
|
|
/// uses "__imp_aux". For other symbols, this means it uses the mangled
|
|
/// ("#" prefix for C) name.
|
|
AArch64II_MO_ARM64EC_CALLMANGLE = 0x800,
|
|
} AArch64II_TOF;
|
|
|
|
// CS namespace end: AArch64II
|
|
|
|
// end namespace AArch64II
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// v8.3a Pointer Authentication
|
|
//
|
|
|
|
// CS namespace begin: AArch64PACKey
|
|
|
|
typedef enum ID {
|
|
AArch64PACKey_IA = 0,
|
|
AArch64PACKey_IB = 1,
|
|
AArch64PACKey_DA = 2,
|
|
AArch64PACKey_DB = 3,
|
|
AArch64PACKey_LAST = AArch64PACKey_DB,
|
|
AArch64PACKey_INVALID,
|
|
} AArch64PACKey_ID;
|
|
|
|
// CS namespace end: AArch64PACKey
|
|
|
|
// namespace AArch64PACKey
|
|
|
|
/// Return 2-letter identifier string for numeric key ID.
|
|
static inline const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID)
|
|
{
|
|
switch (KeyID) {
|
|
default:
|
|
break;
|
|
case AArch64PACKey_IA:
|
|
return "ia";
|
|
case AArch64PACKey_IB:
|
|
return "ib";
|
|
case AArch64PACKey_DA:
|
|
return "da";
|
|
case AArch64PACKey_DB:
|
|
return "db";
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
/// Return numeric key ID for 2-letter identifier string.
|
|
static inline AArch64PACKey_ID AArch64StringToPACKeyID(const char *Name)
|
|
{
|
|
if (strcmp(Name, "ia") == 0)
|
|
return AArch64PACKey_IA;
|
|
if (strcmp(Name, "ib") == 0)
|
|
return AArch64PACKey_IB;
|
|
if (strcmp(Name, "da") == 0)
|
|
return AArch64PACKey_DA;
|
|
if (strcmp(Name, "db") == 0)
|
|
return AArch64PACKey_DB;
|
|
CS_ASSERT_RET_VAL(0 && "Invalid PAC key", AArch64PACKey_INVALID);
|
|
return AArch64PACKey_LAST;
|
|
}
|
|
|
|
// CS namespace begin: AArch64
|
|
|
|
// The number of bits in a SVE register is architecturally defined
|
|
// to be a multiple of this value. If <M x t> has this number of bits,
|
|
// a <n x M x t> vector can be stored in a SVE register without any
|
|
// redundant bits. If <M x t> has this number of bits divided by P,
|
|
// a <n x M x t> vector is stored in a SVE register by placing index i
|
|
// in index i*P of a <n x (M*P) x t> vector. The other elements of the
|
|
// <n x (M*P) x t> vector (such as index 1) are undefined.
|
|
static const unsigned SVEBitsPerBlock = 128;
|
|
|
|
static const unsigned SVEMaxBitsPerVector = 2048;
|
|
|
|
// CS namespace end: AArch64
|
|
|
|
// end namespace AArch64
|
|
// end namespace llvm
|
|
|
|
#endif
|