552 lines
12 KiB
C
552 lines
12 KiB
C
/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifdef CAPSTONE_HAS_ARM
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#include <stdio.h> // debug
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#include <string.h>
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#include "../../cs_priv.h"
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#include "ARMMapping.h"
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#define GET_INSTRINFO_ENUM
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#include "ARMGenInstrInfo.inc"
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#ifndef CAPSTONE_DIET
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static const name_map reg_name_maps[] = {
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{ ARM_REG_INVALID, NULL },
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{ ARM_REG_APSR, "apsr"},
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{ ARM_REG_APSR_NZCV, "apsr_nzcv"},
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{ ARM_REG_CPSR, "cpsr"},
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{ ARM_REG_FPEXC, "fpexc"},
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{ ARM_REG_FPINST, "fpinst"},
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{ ARM_REG_FPSCR, "fpscr"},
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{ ARM_REG_FPSCR_NZCV, "fpscr_nzcv"},
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{ ARM_REG_FPSID, "fpsid"},
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{ ARM_REG_ITSTATE, "itstate"},
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{ ARM_REG_LR, "lr"},
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{ ARM_REG_PC, "pc"},
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{ ARM_REG_SP, "sp"},
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{ ARM_REG_SPSR, "spsr"},
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{ ARM_REG_D0, "d0"},
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{ ARM_REG_D1, "d1"},
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{ ARM_REG_D2, "d2"},
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{ ARM_REG_D3, "d3"},
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{ ARM_REG_D4, "d4"},
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{ ARM_REG_D5, "d5"},
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{ ARM_REG_D6, "d6"},
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{ ARM_REG_D7, "d7"},
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{ ARM_REG_D8, "d8"},
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{ ARM_REG_D9, "d9"},
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{ ARM_REG_D10, "d10"},
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{ ARM_REG_D11, "d11"},
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{ ARM_REG_D12, "d12"},
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{ ARM_REG_D13, "d13"},
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{ ARM_REG_D14, "d14"},
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{ ARM_REG_D15, "d15"},
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{ ARM_REG_D16, "d16"},
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{ ARM_REG_D17, "d17"},
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{ ARM_REG_D18, "d18"},
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{ ARM_REG_D19, "d19"},
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{ ARM_REG_D20, "d20"},
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{ ARM_REG_D21, "d21"},
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{ ARM_REG_D22, "d22"},
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{ ARM_REG_D23, "d23"},
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{ ARM_REG_D24, "d24"},
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{ ARM_REG_D25, "d25"},
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{ ARM_REG_D26, "d26"},
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{ ARM_REG_D27, "d27"},
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{ ARM_REG_D28, "d28"},
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{ ARM_REG_D29, "d29"},
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{ ARM_REG_D30, "d30"},
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{ ARM_REG_D31, "d31"},
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{ ARM_REG_FPINST2, "fpinst2"},
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{ ARM_REG_MVFR0, "mvfr0"},
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{ ARM_REG_MVFR1, "mvfr1"},
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{ ARM_REG_MVFR2, "mvfr2"},
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{ ARM_REG_Q0, "q0"},
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{ ARM_REG_Q1, "q1"},
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{ ARM_REG_Q2, "q2"},
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{ ARM_REG_Q3, "q3"},
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{ ARM_REG_Q4, "q4"},
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{ ARM_REG_Q5, "q5"},
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{ ARM_REG_Q6, "q6"},
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{ ARM_REG_Q7, "q7"},
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{ ARM_REG_Q8, "q8"},
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{ ARM_REG_Q9, "q9"},
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{ ARM_REG_Q10, "q10"},
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{ ARM_REG_Q11, "q11"},
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{ ARM_REG_Q12, "q12"},
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{ ARM_REG_Q13, "q13"},
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{ ARM_REG_Q14, "q14"},
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{ ARM_REG_Q15, "q15"},
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{ ARM_REG_R0, "r0"},
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{ ARM_REG_R1, "r1"},
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{ ARM_REG_R2, "r2"},
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{ ARM_REG_R3, "r3"},
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{ ARM_REG_R4, "r4"},
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{ ARM_REG_R5, "r5"},
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{ ARM_REG_R6, "r6"},
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{ ARM_REG_R7, "r7"},
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{ ARM_REG_R8, "r8"},
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{ ARM_REG_R9, "sb"},
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{ ARM_REG_R10, "sl"},
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{ ARM_REG_R11, "fp"},
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{ ARM_REG_R12, "ip"},
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{ ARM_REG_S0, "s0"},
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{ ARM_REG_S1, "s1"},
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{ ARM_REG_S2, "s2"},
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{ ARM_REG_S3, "s3"},
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{ ARM_REG_S4, "s4"},
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{ ARM_REG_S5, "s5"},
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{ ARM_REG_S6, "s6"},
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{ ARM_REG_S7, "s7"},
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{ ARM_REG_S8, "s8"},
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{ ARM_REG_S9, "s9"},
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{ ARM_REG_S10, "s10"},
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{ ARM_REG_S11, "s11"},
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{ ARM_REG_S12, "s12"},
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{ ARM_REG_S13, "s13"},
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{ ARM_REG_S14, "s14"},
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{ ARM_REG_S15, "s15"},
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{ ARM_REG_S16, "s16"},
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{ ARM_REG_S17, "s17"},
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{ ARM_REG_S18, "s18"},
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{ ARM_REG_S19, "s19"},
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{ ARM_REG_S20, "s20"},
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{ ARM_REG_S21, "s21"},
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{ ARM_REG_S22, "s22"},
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{ ARM_REG_S23, "s23"},
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{ ARM_REG_S24, "s24"},
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{ ARM_REG_S25, "s25"},
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{ ARM_REG_S26, "s26"},
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{ ARM_REG_S27, "s27"},
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{ ARM_REG_S28, "s28"},
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{ ARM_REG_S29, "s29"},
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{ ARM_REG_S30, "s30"},
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{ ARM_REG_S31, "s31"},
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};
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static const name_map reg_name_maps2[] = {
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{ ARM_REG_INVALID, NULL },
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{ ARM_REG_APSR, "apsr"},
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{ ARM_REG_APSR_NZCV, "apsr_nzcv"},
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{ ARM_REG_CPSR, "cpsr"},
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{ ARM_REG_FPEXC, "fpexc"},
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{ ARM_REG_FPINST, "fpinst"},
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{ ARM_REG_FPSCR, "fpscr"},
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{ ARM_REG_FPSCR_NZCV, "fpscr_nzcv"},
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{ ARM_REG_FPSID, "fpsid"},
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{ ARM_REG_ITSTATE, "itstate"},
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{ ARM_REG_LR, "lr"},
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{ ARM_REG_PC, "pc"},
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{ ARM_REG_SP, "sp"},
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{ ARM_REG_SPSR, "spsr"},
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{ ARM_REG_D0, "d0"},
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{ ARM_REG_D1, "d1"},
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{ ARM_REG_D2, "d2"},
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{ ARM_REG_D3, "d3"},
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{ ARM_REG_D4, "d4"},
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{ ARM_REG_D5, "d5"},
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{ ARM_REG_D6, "d6"},
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{ ARM_REG_D7, "d7"},
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{ ARM_REG_D8, "d8"},
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{ ARM_REG_D9, "d9"},
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{ ARM_REG_D10, "d10"},
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{ ARM_REG_D11, "d11"},
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{ ARM_REG_D12, "d12"},
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{ ARM_REG_D13, "d13"},
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{ ARM_REG_D14, "d14"},
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{ ARM_REG_D15, "d15"},
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{ ARM_REG_D16, "d16"},
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{ ARM_REG_D17, "d17"},
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{ ARM_REG_D18, "d18"},
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{ ARM_REG_D19, "d19"},
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{ ARM_REG_D20, "d20"},
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{ ARM_REG_D21, "d21"},
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{ ARM_REG_D22, "d22"},
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{ ARM_REG_D23, "d23"},
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{ ARM_REG_D24, "d24"},
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{ ARM_REG_D25, "d25"},
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{ ARM_REG_D26, "d26"},
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{ ARM_REG_D27, "d27"},
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{ ARM_REG_D28, "d28"},
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{ ARM_REG_D29, "d29"},
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{ ARM_REG_D30, "d30"},
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{ ARM_REG_D31, "d31"},
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{ ARM_REG_FPINST2, "fpinst2"},
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{ ARM_REG_MVFR0, "mvfr0"},
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{ ARM_REG_MVFR1, "mvfr1"},
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{ ARM_REG_MVFR2, "mvfr2"},
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{ ARM_REG_Q0, "q0"},
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{ ARM_REG_Q1, "q1"},
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{ ARM_REG_Q2, "q2"},
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{ ARM_REG_Q3, "q3"},
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{ ARM_REG_Q4, "q4"},
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{ ARM_REG_Q5, "q5"},
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{ ARM_REG_Q6, "q6"},
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{ ARM_REG_Q7, "q7"},
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{ ARM_REG_Q8, "q8"},
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{ ARM_REG_Q9, "q9"},
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{ ARM_REG_Q10, "q10"},
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{ ARM_REG_Q11, "q11"},
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{ ARM_REG_Q12, "q12"},
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{ ARM_REG_Q13, "q13"},
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{ ARM_REG_Q14, "q14"},
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{ ARM_REG_Q15, "q15"},
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{ ARM_REG_R0, "r0"},
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{ ARM_REG_R1, "r1"},
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{ ARM_REG_R2, "r2"},
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{ ARM_REG_R3, "r3"},
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{ ARM_REG_R4, "r4"},
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{ ARM_REG_R5, "r5"},
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{ ARM_REG_R6, "r6"},
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{ ARM_REG_R7, "r7"},
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{ ARM_REG_R8, "r8"},
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{ ARM_REG_R9, "r9"},
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{ ARM_REG_R10, "r10"},
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{ ARM_REG_R11, "r11"},
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{ ARM_REG_R12, "r12"},
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{ ARM_REG_S0, "s0"},
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{ ARM_REG_S1, "s1"},
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{ ARM_REG_S2, "s2"},
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{ ARM_REG_S3, "s3"},
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{ ARM_REG_S4, "s4"},
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{ ARM_REG_S5, "s5"},
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{ ARM_REG_S6, "s6"},
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{ ARM_REG_S7, "s7"},
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{ ARM_REG_S8, "s8"},
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{ ARM_REG_S9, "s9"},
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{ ARM_REG_S10, "s10"},
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{ ARM_REG_S11, "s11"},
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{ ARM_REG_S12, "s12"},
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{ ARM_REG_S13, "s13"},
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{ ARM_REG_S14, "s14"},
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{ ARM_REG_S15, "s15"},
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{ ARM_REG_S16, "s16"},
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{ ARM_REG_S17, "s17"},
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{ ARM_REG_S18, "s18"},
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{ ARM_REG_S19, "s19"},
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{ ARM_REG_S20, "s20"},
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{ ARM_REG_S21, "s21"},
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{ ARM_REG_S22, "s22"},
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{ ARM_REG_S23, "s23"},
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{ ARM_REG_S24, "s24"},
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{ ARM_REG_S25, "s25"},
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{ ARM_REG_S26, "s26"},
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{ ARM_REG_S27, "s27"},
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{ ARM_REG_S28, "s28"},
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{ ARM_REG_S29, "s29"},
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{ ARM_REG_S30, "s30"},
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{ ARM_REG_S31, "s31"},
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};
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#endif
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const char *ARM_reg_name(csh handle, unsigned int reg)
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{
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#ifndef CAPSTONE_DIET
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if (reg >= ARR_SIZE(reg_name_maps))
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return NULL;
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return reg_name_maps[reg].name;
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#else
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return NULL;
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#endif
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}
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const char *ARM_reg_name2(csh handle, unsigned int reg)
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{
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#ifndef CAPSTONE_DIET
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if (reg >= ARR_SIZE(reg_name_maps2))
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return NULL;
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return reg_name_maps2[reg].name;
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#else
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return NULL;
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#endif
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}
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static const insn_map insns[] = {
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// dummy item
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{
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0, 0,
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { 0 }, 0, 0
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#endif
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},
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#include "ARMMappingInsn.inc"
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};
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// look for @id in @insns
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// return -1 if not found
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static unsigned int find_insn(unsigned int id)
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{
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// binary searching since the IDs are sorted in order
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unsigned int left, right, m;
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unsigned int max = ARR_SIZE(insns);
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right = max - 1;
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if (id < insns[0].id || id > insns[right].id)
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// not found
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return -1;
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left = 0;
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while(left <= right) {
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m = (left + right) / 2;
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if (id == insns[m].id) {
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return m;
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}
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if (id < insns[m].id)
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right = m - 1;
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else
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left = m + 1;
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}
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// not found
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// printf("NOT FOUNDDDDDDDDDDDDDDD id = %u\n", id);
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return -1;
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}
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void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
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{
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unsigned int i = find_insn(id);
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if (i != -1) {
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insn->id = insns[i].mapid;
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// printf("id = %u, mapid = %u\n", id, insn->id);
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if (h->detail) {
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#ifndef CAPSTONE_DIET
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cs_struct handle;
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handle.detail = h->detail;
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memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
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insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
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memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
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insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
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memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
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insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
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insn->detail->arm.update_flags = cs_reg_write((csh)&handle, insn, ARM_REG_CPSR);
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if (insns[i].branch || insns[i].indirect_branch) {
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// this insn also belongs to JUMP group. add JUMP group
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insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP;
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insn->detail->groups_count++;
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}
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#endif
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}
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}
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}
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#ifndef CAPSTONE_DIET
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static const char * const insn_name_maps[] = {
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NULL, // ARM_INS_INVALID
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#include "ARMMappingInsnName.inc"
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};
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#endif
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const char *ARM_insn_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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if (id >= ARM_INS_ENDING)
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return NULL;
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return insn_name_maps[id];
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#else
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return NULL;
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#endif
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}
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#ifndef CAPSTONE_DIET
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static const name_map group_name_maps[] = {
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// generic groups
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{ ARM_GRP_INVALID, NULL },
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{ ARM_GRP_JUMP, "jump" },
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{ ARM_GRP_CALL, "call" },
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{ ARM_GRP_INT, "int" },
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{ ARM_GRP_PRIVILEGE, "privilege" },
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{ ARM_GRP_BRANCH_RELATIVE, "branch_relative" },
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// architecture-specific groups
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{ ARM_GRP_CRYPTO, "crypto" },
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{ ARM_GRP_DATABARRIER, "databarrier" },
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{ ARM_GRP_DIVIDE, "divide" },
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{ ARM_GRP_FPARMV8, "fparmv8" },
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{ ARM_GRP_MULTPRO, "multpro" },
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{ ARM_GRP_NEON, "neon" },
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{ ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK" },
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{ ARM_GRP_THUMB2DSP, "THUMB2DSP" },
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{ ARM_GRP_TRUSTZONE, "TRUSTZONE" },
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{ ARM_GRP_V4T, "v4t" },
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{ ARM_GRP_V5T, "v5t" },
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{ ARM_GRP_V5TE, "v5te" },
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{ ARM_GRP_V6, "v6" },
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{ ARM_GRP_V6T2, "v6t2" },
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{ ARM_GRP_V7, "v7" },
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{ ARM_GRP_V8, "v8" },
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{ ARM_GRP_VFP2, "vfp2" },
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{ ARM_GRP_VFP3, "vfp3" },
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{ ARM_GRP_VFP4, "vfp4" },
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{ ARM_GRP_ARM, "arm" },
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{ ARM_GRP_MCLASS, "mclass" },
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{ ARM_GRP_NOTMCLASS, "notmclass" },
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{ ARM_GRP_THUMB, "thumb" },
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{ ARM_GRP_THUMB1ONLY, "thumb1only" },
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{ ARM_GRP_THUMB2, "thumb2" },
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{ ARM_GRP_PREV8, "prev8" },
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{ ARM_GRP_FPVMLX, "fpvmlx" },
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{ ARM_GRP_MULOPS, "mulops" },
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{ ARM_GRP_CRC, "crc" },
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{ ARM_GRP_DPVFP, "dpvfp" },
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{ ARM_GRP_V6M, "v6m" },
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{ ARM_GRP_VIRTUALIZATION, "virtualization" },
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};
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#endif
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const char *ARM_group_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
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#else
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return NULL;
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#endif
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}
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// list all relative branch instructions
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// ie: insns[i].branch && !insns[i].indirect_branch
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static const unsigned int insn_rel[] = {
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ARM_BL,
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ARM_BLX_pred,
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ARM_Bcc,
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ARM_t2B,
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ARM_t2Bcc,
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ARM_tB,
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ARM_tBcc,
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ARM_tCBNZ,
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ARM_tCBZ,
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ARM_BL_pred,
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ARM_BLXi,
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ARM_tBL,
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ARM_tBLXi,
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0
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};
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static const unsigned int insn_blx_rel_to_arm[] = {
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ARM_tBLXi,
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0
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};
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// check if this insn is relative branch
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bool ARM_rel_branch(cs_struct *h, unsigned int id)
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{
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int i;
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for (i = 0; insn_rel[i]; i++) {
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if (id == insn_rel[i]) {
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return true;
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}
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}
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// not found
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return false;
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}
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bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) {
|
|
int i;
|
|
|
|
for (i = 0; insn_blx_rel_to_arm[i]; i++)
|
|
if (id == insn_blx_rel_to_arm[i])
|
|
return true;
|
|
|
|
// not found
|
|
return false;
|
|
|
|
}
|
|
|
|
#ifndef CAPSTONE_DIET
|
|
// map instruction to its characteristics
|
|
typedef struct insn_op {
|
|
uint8_t access[7];
|
|
} insn_op;
|
|
|
|
static const insn_op insn_ops[] = {
|
|
{
|
|
// NULL item
|
|
{ 0 }
|
|
},
|
|
|
|
#include "ARMMappingInsnOp.inc"
|
|
};
|
|
|
|
// given internal insn id, return operand access info
|
|
const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id)
|
|
{
|
|
int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
|
|
if (i != 0) {
|
|
return insn_ops[i].access;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
void ARM_reg_access(const cs_insn *insn,
|
|
cs_regs regs_read, uint8_t *regs_read_count,
|
|
cs_regs regs_write, uint8_t *regs_write_count)
|
|
{
|
|
uint8_t i;
|
|
uint8_t read_count, write_count;
|
|
cs_arm *arm = &(insn->detail->arm);
|
|
|
|
read_count = insn->detail->regs_read_count;
|
|
write_count = insn->detail->regs_write_count;
|
|
|
|
// implicit registers
|
|
memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0]));
|
|
memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0]));
|
|
|
|
// explicit registers
|
|
for (i = 0; i < arm->op_count; i++) {
|
|
cs_arm_op *op = &(arm->operands[i]);
|
|
switch((int)op->type) {
|
|
case ARM_OP_REG:
|
|
if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
|
|
regs_read[read_count] = (uint16_t)op->reg;
|
|
read_count++;
|
|
}
|
|
if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
|
|
regs_write[write_count] = (uint16_t)op->reg;
|
|
write_count++;
|
|
}
|
|
break;
|
|
case ARM_OP_MEM:
|
|
// registers appeared in memory references always being read
|
|
if ((op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
|
|
regs_read[read_count] = (uint16_t)op->mem.base;
|
|
read_count++;
|
|
}
|
|
if ((op->mem.index != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
|
|
regs_read[read_count] = (uint16_t)op->mem.index;
|
|
read_count++;
|
|
}
|
|
if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) {
|
|
regs_write[write_count] = (uint16_t)op->mem.base;
|
|
write_count++;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
*regs_read_count = read_count;
|
|
*regs_write_count = write_count;
|
|
}
|
|
#endif
|
|
|
|
#endif
|