capstone/cstool
z a012f75754 RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h

* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction

* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h

* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter

* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h

* Backport it from: 0db412ce3b

* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.

* Add refactored cs.c for RISCV

* Testing all I instructions in test_riscv.c

* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture

* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c

* fixed bug related to incorrect initialization of memory after malloc

* fix compile bug

* Fix compile errors.

* move riscv.h to include/capstone

* fix indentation issues

* fix coding style issues

* Fix indentation issues

* fix coding style

* Move variable declaration to the top of the block

* Fix coding indentation

* Move some stuff into RISCVMappingInsn.inc

* Fix code sytle

* remove cs_mode support for RISCV

* update asmwriter-inc to LLVM upstream

* update the .inc files to riscv upstream

* update riscv disassembler function for suport 16bit instructions

* update printer & tablegen inc files which have fixed arguments mismatch

* update headers and mapping source

* add riscv architecture specific test code

* fix all RISCV tons of compiler errors

* pass final tests

* add riscv tablegen patchs

* merge with upstream/next

* fix cstool missing riscv file

* fix root Makefile

* add new TableGen patchs for riscv

* fix cmakefile.txt of missing one riscv file

* fix declaration conflict

* fix incompatible declaration type

* change riscvc from arch to mode

* fix test_riscv warnning

* fix code style and add riscv part of test_basic

* add RISCV64 mode

* add suite for riscv

* crack fuzz test

* fix getfeaturebits test add riscvc

* fix test missing const qualifier warnning

* fix testcase type mismatch

* fix return value missing

* change getfeaturebits test

* add test cs files

* using a winder type contain the decode string

* fix a copy typo

* remove useless mode for riscv

* change cs file blank type

* add repo for update_riscv & fix cstool missing riscv mode

* fix typo

* add riscv for cstool useage

* add TableGen patch for riscv asmwriter

* clean ctags file

* remove black comment line

* fix fuzz related something

* fix missing RISCV string of fuzz

* update readme, etc..

* add riscv *.s.cs file

* add riscv *.s.cs file & clear ctags

* clear useless array declarations at capstone_test

* update to 5e4069f

* update readme change name more formal

* change position of riscv after bpf and modify copyright more uniform

* clear useless ctags file

* change blank with tab in riscv.h

* add riscv python bindings

* add riscv in __init__.py

* fix riscv define value for python binding

* fix test_riscv.py typo

* add missing riscvc in __init__.py of python bindings

* fix alias-insn printer bug, remove useless newline

* change inst print delimter from tab to bankspace for travis

* add riscv tablegen patch

* fix inst output more consistency

* add TableGen patch which fix inst output formal

* crack the effective address output for detail and change register print function

* fix not detail crash bug

* change item declaration position at cs_riscv

* update riscv.py

* change function name more meaningfull

* update python binding makefile

* fix register enum sequence according to riscvgenreginfo.inc

* test function name

* add enum s0/fp in riscv.h & update riscv_const.py

* add register name enum
2019-03-09 08:41:12 +08:00
..
Makefile cstool: move code from getopt.h to getopt.c 2019-02-03 14:34:20 +08:00
README merge next to master 2018-07-20 12:36:50 +08:00
cstool.c RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
cstool_arm.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_arm64.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_bpf.c New architecture: BPF (#1388) 2019-02-18 17:39:51 +08:00
cstool_evm.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_m68k.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_m680x.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_mips.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_mos65xx.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_ppc.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_riscv.c RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
cstool_sparc.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_systemz.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_tms320c64x.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_wasm.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_x86.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
cstool_xcore.c wasm: silence some compilation warnings 2019-02-02 00:13:52 +08:00
getopt.c cstool: move code from getopt.h to getopt.c 2019-02-03 14:34:20 +08:00
getopt.h cstool: move code from getopt.h to getopt.c 2019-02-03 14:34:20 +08:00

README

This directory contains cstool of Capstone Engine.

Cstool is a command-line tool to disassemble assembly hex-string.
For example, to decode a hexcode string for Intel 32bit, run:

	$ cstool x32 "90 91"

	0	90	nop
	1	91	xchg	eax, ecx

Cstool disassembles the input and prints out the assembly instructions.
On each line, the first column is the instruction offset, the second
column is opcodes, and the rest is the instruction itself.

Cstool is flexible enough to accept all kind of hexcode format. The following
inputs have the same output with the example above.

	$ cstool x32 "0x90 0x91"
	$ cstool x32 "\x90\x91"
	$ cstool x32 "90,91"
	$ cstool x32 "90;91"
	$ cstool x32 "90+91"
	$ cstool x32 "90:91"

To print out instruction details, run Cstool with -d option, like below.

	$ cstool -d x32 "01 d8"
	0  01d8                              add	eax, ebx
	Prefix:0x00 0x00 0x00 0x00
	Opcode:0x01 0x00 0x00 0x00
	rex: 0x0
	addr_size: 4
	modrm: 0xd8
	disp: 0x0
	sib: 0x0
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[0].access: READ | WRITE
		operands[1].type: REG = ebx
		operands[1].size: 4
		operands[1].access: READ
		Registers read: eax ebx
	Registers modified: eflags eax
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

To see all the supported options, run ./cstool