capstone/tests
z a012f75754 RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h

* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction

* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h

* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter

* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h

* Backport it from: 0db412ce3b

* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.

* Add refactored cs.c for RISCV

* Testing all I instructions in test_riscv.c

* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture

* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c

* fixed bug related to incorrect initialization of memory after malloc

* fix compile bug

* Fix compile errors.

* move riscv.h to include/capstone

* fix indentation issues

* fix coding style issues

* Fix indentation issues

* fix coding style

* Move variable declaration to the top of the block

* Fix coding indentation

* Move some stuff into RISCVMappingInsn.inc

* Fix code sytle

* remove cs_mode support for RISCV

* update asmwriter-inc to LLVM upstream

* update the .inc files to riscv upstream

* update riscv disassembler function for suport 16bit instructions

* update printer & tablegen inc files which have fixed arguments mismatch

* update headers and mapping source

* add riscv architecture specific test code

* fix all RISCV tons of compiler errors

* pass final tests

* add riscv tablegen patchs

* merge with upstream/next

* fix cstool missing riscv file

* fix root Makefile

* add new TableGen patchs for riscv

* fix cmakefile.txt of missing one riscv file

* fix declaration conflict

* fix incompatible declaration type

* change riscvc from arch to mode

* fix test_riscv warnning

* fix code style and add riscv part of test_basic

* add RISCV64 mode

* add suite for riscv

* crack fuzz test

* fix getfeaturebits test add riscvc

* fix test missing const qualifier warnning

* fix testcase type mismatch

* fix return value missing

* change getfeaturebits test

* add test cs files

* using a winder type contain the decode string

* fix a copy typo

* remove useless mode for riscv

* change cs file blank type

* add repo for update_riscv & fix cstool missing riscv mode

* fix typo

* add riscv for cstool useage

* add TableGen patch for riscv asmwriter

* clean ctags file

* remove black comment line

* fix fuzz related something

* fix missing RISCV string of fuzz

* update readme, etc..

* add riscv *.s.cs file

* add riscv *.s.cs file & clear ctags

* clear useless array declarations at capstone_test

* update to 5e4069f

* update readme change name more formal

* change position of riscv after bpf and modify copyright more uniform

* clear useless ctags file

* change blank with tab in riscv.h

* add riscv python bindings

* add riscv in __init__.py

* fix riscv define value for python binding

* fix test_riscv.py typo

* add missing riscvc in __init__.py of python bindings

* fix alias-insn printer bug, remove useless newline

* change inst print delimter from tab to bankspace for travis

* add riscv tablegen patch

* fix inst output more consistency

* add TableGen patch which fix inst output formal

* crack the effective address output for detail and change register print function

* fix not detail crash bug

* change item declaration position at cs_riscv

* update riscv.py

* change function name more meaningfull

* update python binding makefile

* fix register enum sequence according to riscvgenreginfo.inc

* test function name

* add enum s0/fp in riscv.h & update riscv_const.py

* add register name enum
2019-03-09 08:41:12 +08:00
..
Makefile RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
README port Windows driver support 2016-05-11 21:48:32 -07:00
test_arm.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00
test_arm64.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00
test_basic.c RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
test_bpf.c New architecture: BPF (#1388) 2019-02-18 17:39:51 +08:00
test_customized_mnem.c port Windows driver support 2016-05-11 21:48:32 -07:00
test_detail.c New architecture: BPF (#1388) 2019-02-18 17:39:51 +08:00
test_evm.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00
test_iter.c RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
test_m68k.c [M68K] store correct register value in op.reg_pair (#1411) 2019-03-02 17:40:29 +08:00
test_m680x.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00
test_mips.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00
test_mos65xx.c MOS65XX: Fix instruction length for indirect addressing modes (#1402) 2019-02-28 07:39:59 +08:00
test_ppc.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00
test_riscv.c RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
test_skipdata.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00
test_sparc.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00
test_systemz.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00
test_tms320c64x.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00
test_wasm.c wasm: cs_arch_init[] setup WASM in the wrong slot 2019-02-02 23:27:54 +08:00
test_winkernel.cpp fix typo, style 2016-09-28 07:33:14 -07:00
test_x86.c Print EFLAGS and FPU_FLAGS correctly in test_x86 (#1365) 2019-02-05 09:44:06 +08:00
test_xcore.c fix warnings on const char * discards qualifiers 2018-07-24 12:22:10 +08:00

README

This directory contains some test code to show how to use Capstone API.

- test_basic.c
  This code shows the most simple form of API where we only want to get basic
  information out of disassembled instruction, such as address, mnemonic and
  operand string.

- test_detail.c:
  This code shows how to access to architecture-neutral information in disassembled
  instructions, such as implicit registers read/written, or groups of instructions
  that this instruction belong to.

- test_skipdata.c:
  This code shows how to use SKIPDATA option to skip broken instructions (most likely
  some data mixed with instructions) and continue to decode at the next legitimate
  instructions.

- test_iter.c:
  This code shows how to use the API cs_disasm_iter() to decode one instruction at
  a time inside a loop.

- test_customized_mnem.c:
  This code shows how to use MNEMONIC option to customize instruction mnemonic
  at run-time, and then how to reset the engine to use the default mnemonic.

- test_<arch>.c
  These code show how to access architecture-specific information for each
  architecture.

- test_winkernel.cpp
  This code shows how to use Capstone from a Windows driver.