3574 lines
91 KiB
C
3574 lines
91 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
|
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
|
/* Rot127 <unisono@quyllur.org> 2022-2023 */
|
|
/* Automatically generated file by the LLVM TableGen Disassembler Backend. */
|
|
/* Do not edit. */
|
|
|
|
#include <capstone/platform.h>
|
|
#include <assert.h>
|
|
|
|
/// getMnemonic - This method is automatically generated by tablegen
|
|
/// from the instruction set description.
|
|
MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
|
|
static const char AsmStrs[] = {
|
|
/* 0 */ "sub %d15, \0"
|
|
/* 11 */ "add %d15, \0"
|
|
/* 22 */ "and %d15, \0"
|
|
/* 33 */ "jne %d15, \0"
|
|
/* 44 */ "jeq %d15, \0"
|
|
/* 55 */ "or %d15, \0"
|
|
/* 65 */ "jz.t %d15, \0"
|
|
/* 77 */ "jnz.t %d15, \0"
|
|
/* 90 */ "lt %d15, \0"
|
|
/* 100 */ "lt.u %d15, \0"
|
|
/* 112 */ "mov %d15, \0"
|
|
/* 123 */ "jz %d15, \0"
|
|
/* 133 */ "jnz %d15, \0"
|
|
/* 144 */ "sub.a %sp, \0"
|
|
/* 156 */ "ftoq31 \0"
|
|
/* 164 */ "csub.a \0"
|
|
/* 172 */ "subsc.a \0"
|
|
/* 181 */ "addsc.a \0"
|
|
/* 190 */ "difsc.a \0"
|
|
/* 199 */ "cadd.a \0"
|
|
/* 207 */ "ld.a \0"
|
|
/* 213 */ "tlbprobe.a \0"
|
|
/* 225 */ "ge.a \0"
|
|
/* 231 */ "jne.a \0"
|
|
/* 238 */ "addih.a \0"
|
|
/* 247 */ "movh.a \0"
|
|
/* 255 */ "sel.a \0"
|
|
/* 262 */ "csubn.a \0"
|
|
/* 271 */ "caddn.a \0"
|
|
/* 280 */ "seln.a \0"
|
|
/* 288 */ "swap.a \0"
|
|
/* 296 */ "jeq.a \0"
|
|
/* 303 */ "lt.a \0"
|
|
/* 309 */ "st.a \0"
|
|
/* 315 */ "mov.a \0"
|
|
/* 322 */ "nez.a \0"
|
|
/* 329 */ "jz.a \0"
|
|
/* 335 */ "jnz.a \0"
|
|
/* 342 */ "eqz.a \0"
|
|
/* 349 */ "movz.a \0"
|
|
/* 357 */ "mov.aa \0"
|
|
/* 365 */ "ld.da \0"
|
|
/* 372 */ "st.da \0"
|
|
/* 379 */ "lea \0"
|
|
/* 384 */ "lha \0"
|
|
/* 389 */ "sha \0"
|
|
/* 394 */ "ja \0"
|
|
/* 398 */ "jla \0"
|
|
/* 403 */ "fcalla \0"
|
|
/* 411 */ "crc32.b \0"
|
|
/* 420 */ "sha.b \0"
|
|
/* 427 */ "sub.b \0"
|
|
/* 434 */ "add.b \0"
|
|
/* 441 */ "ld.b \0"
|
|
/* 447 */ "absdif.b \0"
|
|
/* 457 */ "sh.b \0"
|
|
/* 463 */ "min.b \0"
|
|
/* 470 */ "clo.b \0"
|
|
/* 477 */ "eq.b \0"
|
|
/* 483 */ "abs.b \0"
|
|
/* 490 */ "subs.b \0"
|
|
/* 498 */ "adds.b \0"
|
|
/* 506 */ "absdifs.b \0"
|
|
/* 517 */ "cls.b \0"
|
|
/* 524 */ "abss.b \0"
|
|
/* 532 */ "sat.b \0"
|
|
/* 539 */ "dvinit.b \0"
|
|
/* 549 */ "lt.b \0"
|
|
/* 555 */ "st.b \0"
|
|
/* 561 */ "max.b \0"
|
|
/* 568 */ "eqany.b \0"
|
|
/* 577 */ "clz.b \0"
|
|
/* 584 */ "csub \0"
|
|
/* 590 */ "msub \0"
|
|
/* 596 */ "rsub \0"
|
|
/* 602 */ "subc \0"
|
|
/* 608 */ "addc \0"
|
|
/* 614 */ "ld.d \0"
|
|
/* 620 */ "st.d \0"
|
|
/* 626 */ "mov.d \0"
|
|
/* 633 */ "cadd \0"
|
|
/* 639 */ "madd \0"
|
|
/* 645 */ "jned \0"
|
|
/* 651 */ "nand \0"
|
|
/* 657 */ "and.ge \0"
|
|
/* 665 */ "sh.ge \0"
|
|
/* 672 */ "xor.ge \0"
|
|
/* 680 */ "jge \0"
|
|
/* 685 */ "bmerge \0"
|
|
/* 693 */ "disable \0"
|
|
/* 702 */ "shuffle \0"
|
|
/* 711 */ "and.ne \0"
|
|
/* 719 */ "xor.ne \0"
|
|
/* 727 */ "jne \0"
|
|
/* 732 */ "msub.f \0"
|
|
/* 740 */ "madd.f \0"
|
|
/* 748 */ "qseed.f \0"
|
|
/* 757 */ "mul.f \0"
|
|
/* 764 */ "cmp.f \0"
|
|
/* 771 */ "div.f \0"
|
|
/* 778 */ "absdif \0"
|
|
/* 786 */ "q31tof \0"
|
|
/* 794 */ "itof \0"
|
|
/* 800 */ "hptof \0"
|
|
/* 807 */ "utof \0"
|
|
/* 813 */ "sha.h \0"
|
|
/* 820 */ "msub.h \0"
|
|
/* 828 */ "msubad.h \0"
|
|
/* 838 */ "madd.h \0"
|
|
/* 846 */ "ld.h \0"
|
|
/* 852 */ "absdif.h \0"
|
|
/* 862 */ "sh.h \0"
|
|
/* 868 */ "mul.h \0"
|
|
/* 875 */ "msubm.h \0"
|
|
/* 884 */ "msubadm.h \0"
|
|
/* 895 */ "maddm.h \0"
|
|
/* 904 */ "mulm.h \0"
|
|
/* 912 */ "maddsum.h \0"
|
|
/* 923 */ "min.h \0"
|
|
/* 930 */ "clo.h \0"
|
|
/* 937 */ "eq.h \0"
|
|
/* 943 */ "msubr.h \0"
|
|
/* 952 */ "msubadr.h \0"
|
|
/* 963 */ "maddr.h \0"
|
|
/* 972 */ "mulr.h \0"
|
|
/* 980 */ "maddsur.h \0"
|
|
/* 991 */ "abs.h \0"
|
|
/* 998 */ "msubs.h \0"
|
|
/* 1007 */ "msubads.h \0"
|
|
/* 1018 */ "madds.h \0"
|
|
/* 1027 */ "absdifs.h \0"
|
|
/* 1038 */ "cls.h \0"
|
|
/* 1045 */ "msubms.h \0"
|
|
/* 1055 */ "msubadms.h \0"
|
|
/* 1067 */ "maddms.h \0"
|
|
/* 1077 */ "mulms.h \0"
|
|
/* 1086 */ "maddsums.h \0"
|
|
/* 1098 */ "msubrs.h \0"
|
|
/* 1108 */ "msubadrs.h \0"
|
|
/* 1120 */ "maddrs.h \0"
|
|
/* 1130 */ "maddsurs.h \0"
|
|
/* 1142 */ "abss.h \0"
|
|
/* 1150 */ "maddsus.h \0"
|
|
/* 1161 */ "sat.h \0"
|
|
/* 1168 */ "dvinit.h \0"
|
|
/* 1178 */ "lt.h \0"
|
|
/* 1184 */ "st.h \0"
|
|
/* 1190 */ "maddsu.h \0"
|
|
/* 1200 */ "max.h \0"
|
|
/* 1207 */ "eqany.h \0"
|
|
/* 1216 */ "clz.h \0"
|
|
/* 1223 */ "addih \0"
|
|
/* 1230 */ "sh \0"
|
|
/* 1234 */ "movh \0"
|
|
/* 1240 */ "tlbprobe.i \0"
|
|
/* 1252 */ "addi \0"
|
|
/* 1258 */ "jnei \0"
|
|
/* 1264 */ "ji \0"
|
|
/* 1268 */ "jli \0"
|
|
/* 1273 */ "fcalli \0"
|
|
/* 1281 */ "ftoi \0"
|
|
/* 1287 */ "dvadj \0"
|
|
/* 1294 */ "unpack \0"
|
|
/* 1302 */ "imask \0"
|
|
/* 1309 */ "sel \0"
|
|
/* 1314 */ "updfl \0"
|
|
/* 1321 */ "jl \0"
|
|
/* 1325 */ "fcall \0"
|
|
/* 1332 */ "syscall \0"
|
|
/* 1341 */ "mul \0"
|
|
/* 1346 */ "msubm \0"
|
|
/* 1353 */ "maddm \0"
|
|
/* 1360 */ "mulm \0"
|
|
/* 1366 */ "crcn \0"
|
|
/* 1372 */ "caddn \0"
|
|
/* 1379 */ "andn \0"
|
|
/* 1385 */ "ixmin \0"
|
|
/* 1392 */ "seln \0"
|
|
/* 1398 */ "orn \0"
|
|
/* 1403 */ "cmovn \0"
|
|
/* 1410 */ "clo \0"
|
|
/* 1415 */ "tlbmap \0"
|
|
/* 1423 */ "tlbdemap \0"
|
|
/* 1433 */ "dvstep \0"
|
|
/* 1441 */ "ftohp \0"
|
|
/* 1448 */ "loop \0"
|
|
/* 1454 */ "msub.q \0"
|
|
/* 1462 */ "madd.q \0"
|
|
/* 1470 */ "ld.q \0"
|
|
/* 1476 */ "mul.q \0"
|
|
/* 1483 */ "msubm.q \0"
|
|
/* 1492 */ "maddm.q \0"
|
|
/* 1501 */ "msubr.q \0"
|
|
/* 1510 */ "maddr.q \0"
|
|
/* 1519 */ "mulr.q \0"
|
|
/* 1527 */ "msubs.q \0"
|
|
/* 1536 */ "madds.q \0"
|
|
/* 1545 */ "msubrs.q \0"
|
|
/* 1555 */ "maddrs.q \0"
|
|
/* 1565 */ "st.q \0"
|
|
/* 1571 */ "and.eq \0"
|
|
/* 1579 */ "sh.eq \0"
|
|
/* 1586 */ "xor.eq \0"
|
|
/* 1594 */ "jeq \0"
|
|
/* 1599 */ "mfcr \0"
|
|
/* 1605 */ "mtcr \0"
|
|
/* 1611 */ "xnor \0"
|
|
/* 1617 */ "xor \0"
|
|
/* 1622 */ "bisr \0"
|
|
/* 1628 */ "dextr \0"
|
|
/* 1635 */ "shas \0"
|
|
/* 1641 */ "abs \0"
|
|
/* 1646 */ "msubs \0"
|
|
/* 1653 */ "rsubs \0"
|
|
/* 1660 */ "madds \0"
|
|
/* 1667 */ "absdifs \0"
|
|
/* 1676 */ "cls \0"
|
|
/* 1681 */ "muls \0"
|
|
/* 1687 */ "msubms \0"
|
|
/* 1695 */ "maddms \0"
|
|
/* 1703 */ "abss \0"
|
|
/* 1709 */ "and.and.t \0"
|
|
/* 1720 */ "sh.and.t \0"
|
|
/* 1730 */ "or.and.t \0"
|
|
/* 1740 */ "sh.nand.t \0"
|
|
/* 1751 */ "and.andn.t \0"
|
|
/* 1763 */ "sh.andn.t \0"
|
|
/* 1774 */ "or.andn.t \0"
|
|
/* 1785 */ "sh.orn.t \0"
|
|
/* 1795 */ "insn.t \0"
|
|
/* 1803 */ "and.or.t \0"
|
|
/* 1813 */ "sh.or.t \0"
|
|
/* 1822 */ "or.or.t \0"
|
|
/* 1831 */ "and.nor.t \0"
|
|
/* 1842 */ "sh.nor.t \0"
|
|
/* 1852 */ "or.nor.t \0"
|
|
/* 1862 */ "sh.xnor.t \0"
|
|
/* 1873 */ "sh.xor.t \0"
|
|
/* 1883 */ "ins.t \0"
|
|
/* 1890 */ "st.t \0"
|
|
/* 1896 */ "jz.t \0"
|
|
/* 1902 */ "jnz.t \0"
|
|
/* 1909 */ "addsc.at \0"
|
|
/* 1919 */ "bsplit \0"
|
|
/* 1927 */ "dvinit \0"
|
|
/* 1935 */ "and.lt \0"
|
|
/* 1943 */ "sh.lt \0"
|
|
/* 1950 */ "xor.lt \0"
|
|
/* 1958 */ "jlt \0"
|
|
/* 1963 */ "not \0"
|
|
/* 1968 */ "insert \0"
|
|
/* 1976 */ "ldmst \0"
|
|
/* 1983 */ "madd.u \0"
|
|
/* 1991 */ "and.ge.u \0"
|
|
/* 2001 */ "sh.ge.u \0"
|
|
/* 2010 */ "xor.ge.u \0"
|
|
/* 2020 */ "jge.u \0"
|
|
/* 2027 */ "mul.u \0"
|
|
/* 2034 */ "msubm.u \0"
|
|
/* 2043 */ "maddm.u \0"
|
|
/* 2052 */ "mulm.u \0"
|
|
/* 2060 */ "ixmin.u \0"
|
|
/* 2069 */ "dvstep.u \0"
|
|
/* 2079 */ "extr.u \0"
|
|
/* 2087 */ "rsubs.u \0"
|
|
/* 2096 */ "madds.u \0"
|
|
/* 2105 */ "muls.u \0"
|
|
/* 2113 */ "msubms.u \0"
|
|
/* 2123 */ "maddms.u \0"
|
|
/* 2133 */ "dvinit.u \0"
|
|
/* 2143 */ "and.lt.u \0"
|
|
/* 2153 */ "sh.lt.u \0"
|
|
/* 2162 */ "xor.lt.u \0"
|
|
/* 2172 */ "jlt.u \0"
|
|
/* 2179 */ "div.u \0"
|
|
/* 2186 */ "mov.u \0"
|
|
/* 2193 */ "ixmax.u \0"
|
|
/* 2202 */ "ld.bu \0"
|
|
/* 2209 */ "min.bu \0"
|
|
/* 2217 */ "subs.bu \0"
|
|
/* 2226 */ "adds.bu \0"
|
|
/* 2235 */ "sat.bu \0"
|
|
/* 2243 */ "dvinit.bu \0"
|
|
/* 2254 */ "lt.bu \0"
|
|
/* 2261 */ "max.bu \0"
|
|
/* 2269 */ "ld.hu \0"
|
|
/* 2276 */ "min.hu \0"
|
|
/* 2284 */ "subs.hu \0"
|
|
/* 2293 */ "adds.hu \0"
|
|
/* 2302 */ "sat.hu \0"
|
|
/* 2310 */ "dvinit.hu \0"
|
|
/* 2321 */ "lt.hu \0"
|
|
/* 2328 */ "max.hu \0"
|
|
/* 2336 */ "ftou \0"
|
|
/* 2342 */ "loopu \0"
|
|
/* 2349 */ "lt.wu \0"
|
|
/* 2356 */ "div \0"
|
|
/* 2361 */ "cmov \0"
|
|
/* 2367 */ "crc32b.w \0"
|
|
/* 2377 */ "ld.w \0"
|
|
/* 2383 */ "swapmsk.w \0"
|
|
/* 2394 */ "crc32l.w \0"
|
|
/* 2404 */ "swap.w \0"
|
|
/* 2412 */ "eq.w \0"
|
|
/* 2418 */ "lt.w \0"
|
|
/* 2424 */ "popcnt.w \0"
|
|
/* 2434 */ "st.w \0"
|
|
/* 2440 */ "ixmax \0"
|
|
/* 2447 */ "subx \0"
|
|
/* 2453 */ "ldlcx \0"
|
|
/* 2460 */ "stlcx \0"
|
|
/* 2467 */ "lducx \0"
|
|
/* 2474 */ "stucx \0"
|
|
/* 2481 */ "addx \0"
|
|
/* 2487 */ "parity \0"
|
|
/* 2495 */ "ftoq31z \0"
|
|
/* 2504 */ "jgez \0"
|
|
/* 2510 */ "jlez \0"
|
|
/* 2516 */ "ftoiz \0"
|
|
/* 2523 */ "jz \0"
|
|
/* 2527 */ "clz \0"
|
|
/* 2532 */ "jnz \0"
|
|
/* 2537 */ "jgtz \0"
|
|
/* 2543 */ "jltz \0"
|
|
/* 2549 */ "ftouz \0"
|
|
/* 2556 */ "swap.a [+\0"
|
|
/* 2566 */ "cachea.i [+\0"
|
|
/* 2578 */ "cachei.i [+\0"
|
|
/* 2590 */ "cachea.wi [+\0"
|
|
/* 2603 */ "cachei.wi [+\0"
|
|
/* 2616 */ "ldmst [+\0"
|
|
/* 2625 */ "cachea.w [+\0"
|
|
/* 2637 */ "cachei.w [+\0"
|
|
/* 2649 */ "cmpswap.w [+\0"
|
|
/* 2662 */ "# XRay Function Patchable RET.\0"
|
|
/* 2693 */ "# XRay Typed Event Log.\0"
|
|
/* 2717 */ "# XRay Custom Event Log.\0"
|
|
/* 2742 */ "# XRay Function Enter.\0"
|
|
/* 2765 */ "# XRay Tail Call Exit.\0"
|
|
/* 2788 */ "# XRay Function Exit.\0"
|
|
/* 2810 */ "LIFETIME_END\0"
|
|
/* 2823 */ "PSEUDO_PROBE\0"
|
|
/* 2836 */ "BUNDLE\0"
|
|
/* 2843 */ "DBG_VALUE\0"
|
|
/* 2853 */ "DBG_INSTR_REF\0"
|
|
/* 2867 */ "DBG_PHI\0"
|
|
/* 2875 */ "DBG_LABEL\0"
|
|
/* 2885 */ "LIFETIME_START\0"
|
|
/* 2900 */ "DBG_VALUE_LIST\0"
|
|
/* 2915 */ "ld.a %a15, [\0"
|
|
/* 2928 */ "ld.b %d15, [\0"
|
|
/* 2941 */ "ld.h %d15, [\0"
|
|
/* 2954 */ "ld.bu %d15, [\0"
|
|
/* 2968 */ "ld.w %d15, [\0"
|
|
/* 2981 */ "swap.a [\0"
|
|
/* 2990 */ "st.a [\0"
|
|
/* 2997 */ "st.da [\0"
|
|
/* 3005 */ "st.b [\0"
|
|
/* 3012 */ "st.d [\0"
|
|
/* 3019 */ "st.h [\0"
|
|
/* 3026 */ "cachea.i [\0"
|
|
/* 3037 */ "cachei.i [\0"
|
|
/* 3048 */ "cachea.wi [\0"
|
|
/* 3060 */ "cachei.wi [\0"
|
|
/* 3072 */ "st.q [\0"
|
|
/* 3079 */ "ldmst [\0"
|
|
/* 3087 */ "cachea.w [\0"
|
|
/* 3098 */ "cachei.w [\0"
|
|
/* 3109 */ "swapmsk.w [\0"
|
|
/* 3121 */ "cmpswap.w [\0"
|
|
/* 3133 */ "st.w [\0"
|
|
/* 3140 */ "ldlcx [\0"
|
|
/* 3148 */ "stlcx [\0"
|
|
/* 3156 */ "lducx [\0"
|
|
/* 3164 */ "stucx [\0"
|
|
/* 3172 */ "st.a [%a15]\0"
|
|
/* 3184 */ "st.b [%a15]\0"
|
|
/* 3196 */ "st.h [%a15]\0"
|
|
/* 3208 */ "st.w [%a15]\0"
|
|
/* 3220 */ "ld.a %a15, [%sp]\0"
|
|
/* 3237 */ "ld.w %a15, [%sp]\0"
|
|
/* 3254 */ "st.a [%sp]\0"
|
|
/* 3265 */ "st.w [%sp]\0"
|
|
/* 3276 */ "tlbflush.a\0"
|
|
/* 3287 */ "tlbflush.b\0"
|
|
/* 3298 */ "dsync\0"
|
|
/* 3304 */ "isync\0"
|
|
/* 3310 */ "rfe\0"
|
|
/* 3314 */ "enable\0"
|
|
/* 3321 */ "disable\0"
|
|
/* 3329 */ "restore\0"
|
|
/* 3337 */ "debug\0"
|
|
/* 3343 */ "relck\0"
|
|
/* 3349 */ "# FEntry call\0"
|
|
/* 3363 */ "rfm\0"
|
|
/* 3367 */ "nop\0"
|
|
/* 3371 */ "fret\0"
|
|
/* 3376 */ "wait\0"
|
|
/* 3381 */ "trapv\0"
|
|
/* 3387 */ "trapsv\0"
|
|
/* 3394 */ "rstv\0"
|
|
/* 3399 */ "svlcx\0"
|
|
};
|
|
static const uint32_t OpInfo0[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
2844U, // DBG_VALUE
|
|
2901U, // DBG_VALUE_LIST
|
|
2854U, // DBG_INSTR_REF
|
|
2868U, // DBG_PHI
|
|
2876U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
2837U, // BUNDLE
|
|
2886U, // LIFETIME_START
|
|
2811U, // LIFETIME_END
|
|
2824U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
3350U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
2743U, // PATCHABLE_FUNCTION_ENTER
|
|
2663U, // PATCHABLE_RET
|
|
2789U, // PATCHABLE_FUNCTION_EXIT
|
|
2766U, // PATCHABLE_TAIL_CALL
|
|
2718U, // PATCHABLE_EVENT_CALL
|
|
2694U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_INTRINSIC_FPTRUNC_ROUND
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_ATOMICRMW_FMAX
|
|
0U, // G_ATOMICRMW_FMIN
|
|
0U, // G_FENCE
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INVOKE_REGION_START
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_IS_FPCLASS
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
4603U, // ABSDIFS_B_rr_v110
|
|
5124U, // ABSDIFS_H_rr
|
|
5764U, // ABSDIFS_rc
|
|
5764U, // ABSDIFS_rr
|
|
4544U, // ABSDIF_B_rr
|
|
4949U, // ABSDIF_H_rr
|
|
268440331U, // ABSDIF_rc
|
|
4875U, // ABSDIF_rr
|
|
17830413U, // ABSS_B_rr_v110
|
|
5239U, // ABSS_H_rr
|
|
17831592U, // ABSS_rr
|
|
16781796U, // ABS_B_rr
|
|
16782304U, // ABS_H_rr
|
|
16782954U, // ABS_rr
|
|
268440161U, // ADDC_rc
|
|
4705U, // ADDC_rr
|
|
536875247U, // ADDIH_A_rlc
|
|
536876232U, // ADDIH_rlc
|
|
805311717U, // ADDI_rlc
|
|
1074796406U, // ADDSC_AT_rr
|
|
6006U, // ADDSC_AT_rr_v110
|
|
1074794678U, // ADDSC_A_rr
|
|
4278U, // ADDSC_A_rr_v110
|
|
33558710U, // ADDSC_A_srrs
|
|
1342181558U, // ADDSC_A_srrs_v110
|
|
6323U, // ADDS_BU_rr_v110
|
|
4595U, // ADDS_B_rr_v110
|
|
5116U, // ADDS_H
|
|
6390U, // ADDS_HU
|
|
6194U, // ADDS_U
|
|
268441650U, // ADDS_U_rc
|
|
268441214U, // ADDS_rc
|
|
5758U, // ADDS_rr
|
|
16782974U, // ADDS_srr
|
|
268442034U, // ADDX_rc
|
|
6578U, // ADDX_rr
|
|
4297U, // ADD_A_rr
|
|
18878665U, // ADD_A_src
|
|
16781513U, // ADD_A_srr
|
|
4531U, // ADD_B_rr
|
|
1664094950U, // ADD_F_rrr
|
|
4936U, // ADD_H_rr
|
|
268440187U, // ADD_rc
|
|
4731U, // ADD_rr
|
|
18879099U, // ADD_src
|
|
18878476U, // ADD_src_15a
|
|
18944635U, // ADD_src_a15
|
|
16781947U, // ADD_srr
|
|
16781324U, // ADD_srr_15a
|
|
16847483U, // ADD_srr_a15
|
|
1879054044U, // ANDN_T
|
|
268440932U, // ANDN_rc
|
|
5476U, // ANDN_rr
|
|
1879054040U, // AND_ANDN_T
|
|
1879053998U, // AND_AND_T
|
|
268441124U, // AND_EQ_rc
|
|
5668U, // AND_EQ_rr
|
|
268441544U, // AND_GE_U_rc
|
|
6088U, // AND_GE_U_rr
|
|
268440210U, // AND_GE_rc
|
|
4754U, // AND_GE_rr
|
|
268441696U, // AND_LT_U_rc
|
|
6240U, // AND_LT_U_rr
|
|
268441488U, // AND_LT_rc
|
|
6032U, // AND_LT_rr
|
|
268440264U, // AND_NE_rc
|
|
4808U, // AND_NE_rr
|
|
1879054120U, // AND_NOR_T
|
|
1879054092U, // AND_OR_T
|
|
1879054002U, // AND_T
|
|
268440205U, // AND_rc
|
|
4749U, // AND_rr
|
|
139287U, // AND_sc
|
|
139287U, // AND_sc_v110
|
|
16781965U, // AND_srr
|
|
16781965U, // AND_srr_v110
|
|
13911U, // BISR_rc
|
|
13911U, // BISR_rc_v161
|
|
140887U, // BISR_sc
|
|
140887U, // BISR_sc_v110
|
|
4782U, // BMERGAE_rr_v110
|
|
4782U, // BMERGE_rr
|
|
16783232U, // BSPLIT_rr
|
|
16783232U, // BSPLIT_rr_v110
|
|
4398035U, // CACHEA_I_bo_bso
|
|
4463571U, // CACHEA_I_bo_c
|
|
4529107U, // CACHEA_I_bo_pos
|
|
4397575U, // CACHEA_I_bo_pre
|
|
400339U, // CACHEA_I_bo_r
|
|
4398057U, // CACHEA_WI_bo_bso
|
|
4463593U, // CACHEA_WI_bo_c
|
|
4529129U, // CACHEA_WI_bo_pos
|
|
4397599U, // CACHEA_WI_bo_pre
|
|
400361U, // CACHEA_WI_bo_r
|
|
4398096U, // CACHEA_W_bo_bso
|
|
4463632U, // CACHEA_W_bo_c
|
|
4529168U, // CACHEA_W_bo_pos
|
|
4397634U, // CACHEA_W_bo_pre
|
|
400400U, // CACHEA_W_bo_r
|
|
4398046U, // CACHEI_I_bo_bso
|
|
4529118U, // CACHEI_I_bo_pos
|
|
4397587U, // CACHEI_I_bo_pre
|
|
4398069U, // CACHEI_WI_bo_bso
|
|
4529141U, // CACHEI_WI_bo_pos
|
|
4397612U, // CACHEI_WI_bo_pre
|
|
4398107U, // CACHEI_W_bo_bso
|
|
4529179U, // CACHEI_W_bo_pos
|
|
4397646U, // CACHEI_W_bo_pre
|
|
1074794768U, // CADDN_A_rcr_v110
|
|
2200965392U, // CADDN_A_rrr_v110
|
|
1074795869U, // CADDN_rcr
|
|
2200966493U, // CADDN_rrr
|
|
18945373U, // CADDN_src
|
|
16848221U, // CADDN_srr_v110
|
|
1074794696U, // CADD_A_rcr_v110
|
|
2200965320U, // CADD_A_rrr_v110
|
|
1074795130U, // CADD_rcr
|
|
2200965754U, // CADD_rrr
|
|
18944634U, // CADD_src
|
|
16847482U, // CADD_srr_v110
|
|
16789U, // CALLA_b
|
|
136443U, // CALLI_rr
|
|
136443U, // CALLI_rr_v110
|
|
17711U, // CALL_b
|
|
21807U, // CALL_sb
|
|
16781783U, // CLO_B_rr_v110
|
|
16782243U, // CLO_H_rr
|
|
16782723U, // CLO_rr
|
|
16781830U, // CLS_B_rr_v110
|
|
16782351U, // CLS_H_rr
|
|
16782989U, // CLS_rr
|
|
16781890U, // CLZ_B_rr_v110
|
|
16782529U, // CLZ_H_rr
|
|
16783840U, // CLZ_rr
|
|
18945404U, // CMOVN_src
|
|
16848252U, // CMOVN_srr
|
|
18946362U, // CMOV_src
|
|
16849210U, // CMOV_srr
|
|
72576050U, // CMPSWAP_W_bo_bso
|
|
72641586U, // CMPSWAP_W_bo_c
|
|
72707122U, // CMPSWAP_W_bo_pos
|
|
72575578U, // CMPSWAP_W_bo_pre
|
|
23555122U, // CMPSWAP_W_bo_r
|
|
4861U, // CMP_F_rr
|
|
1074796864U, // CRC32B_W_rr
|
|
1074796891U, // CRC32L_W_rr
|
|
1074794908U, // CRC32_B_rr
|
|
2200966487U, // CRCN_rrr
|
|
2200965383U, // CSUBN_A__rrr_v110
|
|
2200965705U, // CSUBN_rrr
|
|
2200965285U, // CSUB_A__rrr_v110
|
|
2200965705U, // CSUB_rrr
|
|
3338U, // DEBUG_sr
|
|
3338U, // DEBUG_sys
|
|
5725U, // DEXTR_rrpw
|
|
5725U, // DEXTR_rrrr
|
|
4287U, // DIFSC_A_rr_v110
|
|
3322U, // DISABLE_sys
|
|
135862U, // DISABLE_sys_1
|
|
4868U, // DIV_F_rr
|
|
6276U, // DIV_U_rr
|
|
6453U, // DIV_rr
|
|
3299U, // DSYNC_sys
|
|
87037192U, // DVADJ_rrr
|
|
87037192U, // DVADJ_rrr_v110
|
|
16782600U, // DVADJ_srr_v110
|
|
6340U, // DVINIT_BU_rr
|
|
6340U, // DVINIT_BU_rr_v110
|
|
4636U, // DVINIT_B_rr
|
|
4636U, // DVINIT_B_rr_v110
|
|
6407U, // DVINIT_HU_rr
|
|
6407U, // DVINIT_HU_rr_v110
|
|
5265U, // DVINIT_H_rr
|
|
5265U, // DVINIT_H_rr_v110
|
|
6230U, // DVINIT_U_rr
|
|
6230U, // DVINIT_U_rr_v110
|
|
6024U, // DVINIT_rr
|
|
6024U, // DVINIT_rr_v110
|
|
87037974U, // DVSTEP_U_rrr
|
|
87037974U, // DVSTEP_U_rrrv110
|
|
16783382U, // DVSTEP_Uv110
|
|
87037338U, // DVSTEP_rrr
|
|
87037338U, // DVSTEP_rrrv110
|
|
16782746U, // DVSTEPv110
|
|
3315U, // ENABLE_sys
|
|
268440121U, // EQANY_B_rc
|
|
4665U, // EQANY_B_rr
|
|
268440760U, // EQANY_H_rc
|
|
5304U, // EQANY_H_rr
|
|
16781655U, // EQZ_A_rr
|
|
4394U, // EQ_A_rr
|
|
4574U, // EQ_B_rr
|
|
5034U, // EQ_H_rr
|
|
6509U, // EQ_W_rr
|
|
268441128U, // EQ_rc
|
|
5672U, // EQ_rr
|
|
18878510U, // EQ_src
|
|
16781358U, // EQ_srr
|
|
6176U, // EXTR_U_rrpw
|
|
6176U, // EXTR_U_rrrr
|
|
2415925280U, // EXTR_U_rrrw
|
|
5726U, // EXTR_rrpw
|
|
5726U, // EXTR_rrrr
|
|
2415924830U, // EXTR_rrrw
|
|
16788U, // FCALLA_b
|
|
136442U, // FCALLA_i
|
|
17710U, // FCALL_b
|
|
3372U, // FRET_sr
|
|
3372U, // FRET_sys
|
|
16782754U, // FTOHP_rr
|
|
16783829U, // FTOIZ_rr
|
|
16782594U, // FTOI_rr
|
|
6592U, // FTOQ31Z_rr
|
|
4253U, // FTOQ31_rr
|
|
16783862U, // FTOUZ_rr
|
|
16783649U, // FTOU_rr
|
|
4322U, // GE_A_rr
|
|
268441548U, // GE_U_rc
|
|
6092U, // GE_U_rr
|
|
268440214U, // GE_rc
|
|
4758U, // GE_rr
|
|
16782113U, // HPTOF_rr
|
|
5399U, // IMASK_rcpw
|
|
1074795799U, // IMASK_rcrw
|
|
5399U, // IMASK_rrpw
|
|
2416973079U, // IMASK_rrrw
|
|
6065U, // INSERT_rcpw
|
|
6065U, // INSERT_rcrr
|
|
2415925169U, // INSERT_rcrw
|
|
6065U, // INSERT_rrpw
|
|
6065U, // INSERT_rrrr
|
|
6065U, // INSERT_rrrw
|
|
1879054084U, // INSN_T
|
|
1879054172U, // INS_T
|
|
3305U, // ISYNC_sys
|
|
16782107U, // ITOF_rr
|
|
87038098U, // IXMAX_U_rrr
|
|
87038345U, // IXMAX_rrr
|
|
87037965U, // IXMIN_U_rrr
|
|
87037290U, // IXMIN_rrr
|
|
16779U, // JA_b
|
|
2684358953U, // JEQ_A_brr
|
|
2686457403U, // JEQ_brc
|
|
2684360251U, // JEQ_brr
|
|
28717U, // JEQ_sbc1
|
|
28717U, // JEQ_sbc2
|
|
28717U, // JEQ_sbc_v110
|
|
7344173U, // JEQ_sbr1
|
|
7344173U, // JEQ_sbr2
|
|
7344173U, // JEQ_sbr_v110
|
|
7346633U, // JGEZ_sbr
|
|
7346633U, // JGEZ_sbr_v110
|
|
2692749285U, // JGE_U_brc
|
|
2684360677U, // JGE_U_brr
|
|
2686456489U, // JGE_brc
|
|
2684359337U, // JGE_brr
|
|
7346666U, // JGTZ_sbr
|
|
7346666U, // JGTZ_sbr_v110
|
|
136433U, // JI_rr
|
|
136433U, // JI_rr_v110
|
|
136433U, // JI_sbr_v110
|
|
136433U, // JI_sr
|
|
16783U, // JLA_b
|
|
7346639U, // JLEZ_sbr
|
|
7346639U, // JLEZ_sbr_v110
|
|
136437U, // JLI_rr
|
|
136437U, // JLI_rr_v110
|
|
7346672U, // JLTZ_sbr
|
|
7346672U, // JLTZ_sbr_v110
|
|
2692749437U, // JLT_U_brc
|
|
2684360829U, // JLT_U_brr
|
|
2692749223U, // JLT_brc
|
|
2684360615U, // JLT_brr
|
|
17706U, // JL_b
|
|
2692747910U, // JNED_brc
|
|
2684359302U, // JNED_brr
|
|
2692748523U, // JNEI_brc
|
|
2684359915U, // JNEI_brr
|
|
2684358888U, // JNE_A_brr
|
|
2686456536U, // JNE_brc
|
|
2684359384U, // JNE_brr
|
|
28706U, // JNE_sbc1
|
|
28706U, // JNE_sbc2
|
|
28706U, // JNE_sbc_v110
|
|
7344162U, // JNE_sbr1
|
|
7344162U, // JNE_sbr2
|
|
7344162U, // JNE_sbr_v110
|
|
9441616U, // JNZ_A_brr
|
|
7344464U, // JNZ_A_sbr
|
|
2684360559U, // JNZ_T_brn
|
|
7344206U, // JNZ_T_sbrn
|
|
7344206U, // JNZ_T_sbrn_v110
|
|
20614U, // JNZ_sb
|
|
20614U, // JNZ_sb_v110
|
|
7346661U, // JNZ_sbr
|
|
7346661U, // JNZ_sbr_v110
|
|
9441610U, // JZ_A_brr
|
|
7344458U, // JZ_A_sbr
|
|
2684360553U, // JZ_T_brn
|
|
7344194U, // JZ_T_sbrn
|
|
7344194U, // JZ_T_sbrn_v110
|
|
20604U, // JZ_sb
|
|
20604U, // JZ_sb_v110
|
|
7346652U, // JZ_sbr
|
|
7346652U, // JZ_sbr_v110
|
|
17676U, // J_b
|
|
21772U, // J_sb
|
|
21772U, // J_sb_v110
|
|
166294U, // LDLCX_abs
|
|
4398149U, // LDLCX_bo_bso
|
|
38841U, // LDMST_abs
|
|
72576008U, // LDMST_bo_bso
|
|
72641544U, // LDMST_bo_c
|
|
72707080U, // LDMST_bo_pos
|
|
72575545U, // LDMST_bo_pre
|
|
23555080U, // LDMST_bo_r
|
|
166308U, // LDUCX_abs
|
|
4398165U, // LDUCX_bo_bso
|
|
10490064U, // LD_A_abs
|
|
3053981904U, // LD_A_bo_bso
|
|
117969104U, // LD_A_bo_c
|
|
3087536336U, // LD_A_bo_pos
|
|
3054047440U, // LD_A_bo_pre
|
|
151523536U, // LD_A_bo_r
|
|
906498256U, // LD_A_bol
|
|
142485U, // LD_A_sc
|
|
1711804624U, // LD_A_slr
|
|
1745359056U, // LD_A_slr_post
|
|
1745359056U, // LD_A_slr_post_v110
|
|
1711804624U, // LD_A_slr_v110
|
|
659664U, // LD_A_slro
|
|
659664U, // LD_A_slro_v110
|
|
25369444U, // LD_A_sro
|
|
25369444U, // LD_A_sro_v110
|
|
10492059U, // LD_BU_abs
|
|
3053983899U, // LD_BU_bo_bso
|
|
117971099U, // LD_BU_bo_c
|
|
3087538331U, // LD_BU_bo_pos
|
|
3054049435U, // LD_BU_bo_pre
|
|
151525531U, // LD_BU_bo_r
|
|
906500251U, // LD_BU_bol
|
|
1711806619U, // LD_BU_slr
|
|
1745361051U, // LD_BU_slr_post
|
|
1745361051U, // LD_BU_slr_post_v110
|
|
1711806619U, // LD_BU_slr_v110
|
|
661659U, // LD_BU_slro
|
|
661659U, // LD_BU_slro_v110
|
|
25369483U, // LD_BU_sro
|
|
25369483U, // LD_BU_sro_v110
|
|
10490298U, // LD_B_abs
|
|
3053982138U, // LD_B_bo_bso
|
|
117969338U, // LD_B_bo_c
|
|
3087536570U, // LD_B_bo_pos
|
|
3054047674U, // LD_B_bo_pre
|
|
151523770U, // LD_B_bo_r
|
|
906498490U, // LD_B_bol
|
|
1745359290U, // LD_B_slr_post_v110
|
|
1711804858U, // LD_B_slr_v110
|
|
659898U, // LD_B_slro_v110
|
|
25369457U, // LD_B_sro_v110
|
|
10490222U, // LD_DA_abs
|
|
3053982062U, // LD_DA_bo_bso
|
|
117969262U, // LD_DA_bo_c
|
|
3087536494U, // LD_DA_bo_pos
|
|
3054047598U, // LD_DA_bo_pre
|
|
151523694U, // LD_DA_bo_r
|
|
10490471U, // LD_D_abs
|
|
3053982311U, // LD_D_bo_bso
|
|
117969511U, // LD_D_bo_c
|
|
3087536743U, // LD_D_bo_pos
|
|
3054047847U, // LD_D_bo_pre
|
|
151523943U, // LD_D_bo_r
|
|
10492126U, // LD_HU_abs
|
|
3053983966U, // LD_HU_bo_bso
|
|
117971166U, // LD_HU_bo_c
|
|
3087538398U, // LD_HU_bo_pos
|
|
3054049502U, // LD_HU_bo_pre
|
|
151525598U, // LD_HU_bo_r
|
|
906500318U, // LD_HU_bol
|
|
10490703U, // LD_H_abs
|
|
3053982543U, // LD_H_bo_bso
|
|
117969743U, // LD_H_bo_c
|
|
3087536975U, // LD_H_bo_pos
|
|
3054048079U, // LD_H_bo_pre
|
|
151524175U, // LD_H_bo_r
|
|
906498895U, // LD_H_bol
|
|
1711805263U, // LD_H_slr
|
|
1745359695U, // LD_H_slr_post
|
|
1745359695U, // LD_H_slr_post_v110
|
|
1711805263U, // LD_H_slr_v110
|
|
660303U, // LD_H_slro
|
|
660303U, // LD_H_slro_v110
|
|
25369470U, // LD_H_sro
|
|
25369470U, // LD_H_sro_v110
|
|
10491327U, // LD_Q_abs
|
|
3053983167U, // LD_Q_bo_bso
|
|
117970367U, // LD_Q_bo_c
|
|
3087537599U, // LD_Q_bo_pos
|
|
3054048703U, // LD_Q_bo_pre
|
|
151524799U, // LD_Q_bo_r
|
|
10492234U, // LD_W_abs
|
|
3053984074U, // LD_W_bo_bso
|
|
117971274U, // LD_W_bo_c
|
|
3087538506U, // LD_W_bo_pos
|
|
3054049610U, // LD_W_bo_pre
|
|
151525706U, // LD_W_bo_r
|
|
906500426U, // LD_W_bol
|
|
142502U, // LD_W_sc
|
|
1711806794U, // LD_W_slr
|
|
1745361226U, // LD_W_slr_post
|
|
1745361226U, // LD_W_slr_post_v110
|
|
1711806794U, // LD_W_slr_v110
|
|
661834U, // LD_W_slro
|
|
661834U, // LD_W_slro_v110
|
|
25369497U, // LD_W_sro
|
|
25369497U, // LD_W_sro_v110
|
|
10490236U, // LEA_abs
|
|
3053982076U, // LEA_bo_bso
|
|
906498428U, // LEA_bol
|
|
10490241U, // LHA_abs
|
|
43303U, // LOOPU_brr
|
|
9442729U, // LOOP_brr
|
|
7345577U, // LOOP_sbr
|
|
4400U, // LT_A_rr
|
|
4646U, // LT_B
|
|
6351U, // LT_BU
|
|
5275U, // LT_H
|
|
6418U, // LT_HU
|
|
268441700U, // LT_U_rc
|
|
6244U, // LT_U_rr
|
|
25170021U, // LT_U_srcv110
|
|
16781413U, // LT_U_srrv110
|
|
6515U, // LT_W
|
|
6446U, // LT_WU
|
|
268441492U, // LT_rc
|
|
6036U, // LT_rr
|
|
18878555U, // LT_src
|
|
16781403U, // LT_srr
|
|
2200966188U, // MADDMS_H_rrr1_LL
|
|
2200966188U, // MADDMS_H_rrr1_LU
|
|
2200966188U, // MADDMS_H_rrr1_UL
|
|
2200966188U, // MADDMS_H_rrr1_UU
|
|
1074796620U, // MADDMS_U_rcr_v110
|
|
2200967244U, // MADDMS_U_rrr2_v110
|
|
1074796192U, // MADDMS_rcr_v110
|
|
2200966816U, // MADDMS_rrr2_v110
|
|
2200966016U, // MADDM_H_rrr1_LL
|
|
2200966016U, // MADDM_H_rrr1_LU
|
|
2200966016U, // MADDM_H_rrr1_UL
|
|
2200966016U, // MADDM_H_rrr1_UU
|
|
2200966016U, // MADDM_H_rrr1_v110
|
|
2200966613U, // MADDM_Q_rrr1_v110
|
|
1074796540U, // MADDM_U_rcr_v110
|
|
2200967164U, // MADDM_U_rrr2_v110
|
|
1074795850U, // MADDM_rcr_v110
|
|
2200966474U, // MADDM_rrr2_v110
|
|
2200966241U, // MADDRS_H_rrr1_LL
|
|
2200966241U, // MADDRS_H_rrr1_LU
|
|
2200966241U, // MADDRS_H_rrr1_UL
|
|
2200966241U, // MADDRS_H_rrr1_UL_2
|
|
2200966241U, // MADDRS_H_rrr1_UU
|
|
2200966241U, // MADDRS_H_rrr1_v110
|
|
3274708500U, // MADDRS_Q_rrr1_L_L
|
|
3543143956U, // MADDRS_Q_rrr1_U_U
|
|
2200966676U, // MADDRS_Q_rrr1_v110
|
|
2200966084U, // MADDR_H_rrr1_LL
|
|
2200966084U, // MADDR_H_rrr1_LU
|
|
2200966084U, // MADDR_H_rrr1_UL
|
|
2200966084U, // MADDR_H_rrr1_UL_2
|
|
2200966084U, // MADDR_H_rrr1_UU
|
|
2200966084U, // MADDR_H_rrr1_v110
|
|
3274708455U, // MADDR_Q_rrr1_L_L
|
|
3543143911U, // MADDR_Q_rrr1_U_U
|
|
2200966631U, // MADDR_Q_rrr1_v110
|
|
2200966207U, // MADDSUMS_H_rrr1_LL
|
|
2200966207U, // MADDSUMS_H_rrr1_LU
|
|
2200966207U, // MADDSUMS_H_rrr1_UL
|
|
2200966207U, // MADDSUMS_H_rrr1_UU
|
|
2200966033U, // MADDSUM_H_rrr1_LL
|
|
2200966033U, // MADDSUM_H_rrr1_LU
|
|
2200966033U, // MADDSUM_H_rrr1_UL
|
|
2200966033U, // MADDSUM_H_rrr1_UU
|
|
2200966251U, // MADDSURS_H_rrr1_LL
|
|
2200966251U, // MADDSURS_H_rrr1_LU
|
|
2200966251U, // MADDSURS_H_rrr1_UL
|
|
2200966251U, // MADDSURS_H_rrr1_UU
|
|
2200966101U, // MADDSUR_H_rrr1_LL
|
|
2200966101U, // MADDSUR_H_rrr1_LU
|
|
2200966101U, // MADDSUR_H_rrr1_UL
|
|
2200966101U, // MADDSUR_H_rrr1_UU
|
|
2200966271U, // MADDSUS_H_rrr1_LL
|
|
2200966271U, // MADDSUS_H_rrr1_LU
|
|
2200966271U, // MADDSUS_H_rrr1_UL
|
|
2200966271U, // MADDSUS_H_rrr1_UU
|
|
2200966311U, // MADDSU_H_rrr1_LL
|
|
2200966311U, // MADDSU_H_rrr1_LU
|
|
2200966311U, // MADDSU_H_rrr1_UL
|
|
2200966311U, // MADDSU_H_rrr1_UU
|
|
2200966139U, // MADDS_H_rrr1_LL
|
|
2200966139U, // MADDS_H_rrr1_LU
|
|
2200966139U, // MADDS_H_rrr1_UL
|
|
2200966139U, // MADDS_H_rrr1_UU
|
|
2200966139U, // MADDS_H_rrr1_v110
|
|
2200966657U, // MADDS_Q_rrr1
|
|
2200966657U, // MADDS_Q_rrr1_L
|
|
3274708481U, // MADDS_Q_rrr1_L_L
|
|
2200966657U, // MADDS_Q_rrr1_U
|
|
2200966657U, // MADDS_Q_rrr1_UU2_v110
|
|
3543143937U, // MADDS_Q_rrr1_U_U
|
|
2200966657U, // MADDS_Q_rrr1_e
|
|
2200966657U, // MADDS_Q_rrr1_e_L
|
|
3274708481U, // MADDS_Q_rrr1_e_L_L
|
|
2200966657U, // MADDS_Q_rrr1_e_U
|
|
3543143937U, // MADDS_Q_rrr1_e_U_U
|
|
1074796593U, // MADDS_U_rcr
|
|
1074796593U, // MADDS_U_rcr_e
|
|
2200967217U, // MADDS_U_rrr2
|
|
2200967217U, // MADDS_U_rrr2_e
|
|
1074796157U, // MADDS_rcr
|
|
1074796157U, // MADDS_rcr_e
|
|
2200966781U, // MADDS_rrr2
|
|
2200966781U, // MADDS_rrr2_e
|
|
2200965861U, // MADD_F_rrr
|
|
2200965959U, // MADD_H_rrr1_LL
|
|
2200965959U, // MADD_H_rrr1_LU
|
|
2200965959U, // MADD_H_rrr1_UL
|
|
2200965959U, // MADD_H_rrr1_UU
|
|
2200965959U, // MADD_H_rrr1_v110
|
|
2200966583U, // MADD_Q_rrr1
|
|
2200966583U, // MADD_Q_rrr1_L
|
|
3274708407U, // MADD_Q_rrr1_L_L
|
|
2200966583U, // MADD_Q_rrr1_U
|
|
2200966583U, // MADD_Q_rrr1_UU2_v110
|
|
3543143863U, // MADD_Q_rrr1_U_U
|
|
2200966583U, // MADD_Q_rrr1_e
|
|
2200966583U, // MADD_Q_rrr1_e_L
|
|
3274708407U, // MADD_Q_rrr1_e_L_L
|
|
2200966583U, // MADD_Q_rrr1_e_U
|
|
3543143863U, // MADD_Q_rrr1_e_U_U
|
|
1074796480U, // MADD_U_rcr
|
|
2200967104U, // MADD_U_rrr2
|
|
1074795136U, // MADD_rcr
|
|
1074795136U, // MADD_rcr_e
|
|
2200965760U, // MADD_rrr2
|
|
2200965760U, // MADD_rrr2_e
|
|
4658U, // MAX_B
|
|
6358U, // MAX_BU
|
|
5297U, // MAX_H
|
|
6425U, // MAX_HU
|
|
268441748U, // MAX_U_rc
|
|
6292U, // MAX_U_rr
|
|
268441995U, // MAX_rc
|
|
6539U, // MAX_rr
|
|
11540032U, // MFCR_rlc
|
|
4560U, // MIN_B
|
|
6306U, // MIN_BU
|
|
5020U, // MIN_H
|
|
6373U, // MIN_HU
|
|
268441615U, // MIN_U_rc
|
|
6159U, // MIN_U_rr
|
|
268440940U, // MIN_rc
|
|
5484U, // MIN_rr
|
|
11538680U, // MOVH_A_rlc
|
|
11539667U, // MOVH_rlc
|
|
135518U, // MOVZ_A_sr
|
|
17830246U, // MOV_AA_rr
|
|
16781670U, // MOV_AA_srr_srr
|
|
16781670U, // MOV_AA_srr_srr_v110
|
|
4412U, // MOV_A_rr
|
|
25170236U, // MOV_A_src
|
|
16781628U, // MOV_A_srr
|
|
16781628U, // MOV_A_srr_v110
|
|
17830515U, // MOV_D_rr
|
|
16781939U, // MOV_D_srr_srr
|
|
16781939U, // MOV_D_srr_srr_v110
|
|
11540619U, // MOV_U_rlc
|
|
12589371U, // MOV_rlc
|
|
11540795U, // MOV_rlc_e
|
|
17832251U, // MOV_rr
|
|
17832251U, // MOV_rr_e
|
|
6459U, // MOV_rr_eab
|
|
139377U, // MOV_sc
|
|
139377U, // MOV_sc_v110
|
|
18880827U, // MOV_src
|
|
18880827U, // MOV_src_e
|
|
16783675U, // MOV_srr
|
|
2200966176U, // MSUBADMS_H_rrr1_LL
|
|
2200966176U, // MSUBADMS_H_rrr1_LU
|
|
2200966176U, // MSUBADMS_H_rrr1_UL
|
|
2200966176U, // MSUBADMS_H_rrr1_UU
|
|
2200966005U, // MSUBADM_H_rrr1_LL
|
|
2200966005U, // MSUBADM_H_rrr1_LU
|
|
2200966005U, // MSUBADM_H_rrr1_UL
|
|
2200966005U, // MSUBADM_H_rrr1_UU
|
|
2200966229U, // MSUBADRS_H_rrr1_LL
|
|
2200966229U, // MSUBADRS_H_rrr1_LU
|
|
2200966229U, // MSUBADRS_H_rrr1_UL
|
|
2200966229U, // MSUBADRS_H_rrr1_UU
|
|
2200966229U, // MSUBADRS_H_rrr1_v110
|
|
2200966073U, // MSUBADR_H_rrr1_LL
|
|
2200966073U, // MSUBADR_H_rrr1_LU
|
|
2200966073U, // MSUBADR_H_rrr1_UL
|
|
2200966073U, // MSUBADR_H_rrr1_UU
|
|
2200966073U, // MSUBADR_H_rrr1_v110
|
|
2200966128U, // MSUBADS_H_rrr1_LL
|
|
2200966128U, // MSUBADS_H_rrr1_LU
|
|
2200966128U, // MSUBADS_H_rrr1_UL
|
|
2200966128U, // MSUBADS_H_rrr1_UU
|
|
2200965949U, // MSUBAD_H_rrr1_LL
|
|
2200965949U, // MSUBAD_H_rrr1_LU
|
|
2200965949U, // MSUBAD_H_rrr1_UL
|
|
2200965949U, // MSUBAD_H_rrr1_UU
|
|
2200966166U, // MSUBMS_H_rrr1_LL
|
|
2200966166U, // MSUBMS_H_rrr1_LU
|
|
2200966166U, // MSUBMS_H_rrr1_UL
|
|
2200966166U, // MSUBMS_H_rrr1_UU
|
|
1074796610U, // MSUBMS_U_rcrv110
|
|
2200967234U, // MSUBMS_U_rrr2v110
|
|
1074796184U, // MSUBMS_rcrv110
|
|
2200966808U, // MSUBMS_rrr2v110
|
|
2200965996U, // MSUBM_H_rrr1_LL
|
|
2200965996U, // MSUBM_H_rrr1_LU
|
|
2200965996U, // MSUBM_H_rrr1_UL
|
|
2200965996U, // MSUBM_H_rrr1_UU
|
|
2200965996U, // MSUBM_H_rrr1_v110
|
|
2200966604U, // MSUBM_Q_rrr1_v110
|
|
1074796531U, // MSUBM_U_rcrv110
|
|
2200967155U, // MSUBM_U_rrr2v110
|
|
1074795843U, // MSUBM_rcrv110
|
|
2200966467U, // MSUBM_rrr2v110
|
|
2200966219U, // MSUBRS_H_rrr1_LL
|
|
2200966219U, // MSUBRS_H_rrr1_LU
|
|
2200966219U, // MSUBRS_H_rrr1_UL
|
|
2200966219U, // MSUBRS_H_rrr1_UL_2
|
|
2200966219U, // MSUBRS_H_rrr1_UU
|
|
2200966219U, // MSUBRS_H_rrr1_v110
|
|
3274708490U, // MSUBRS_Q_rrr1_L_L
|
|
3543143946U, // MSUBRS_Q_rrr1_U_U
|
|
2200966666U, // MSUBRS_Q_rrr1_v110
|
|
2200966064U, // MSUBR_H_rrr1_LL
|
|
2200966064U, // MSUBR_H_rrr1_LU
|
|
2200966064U, // MSUBR_H_rrr1_UL
|
|
2200966064U, // MSUBR_H_rrr1_UL_2
|
|
2200966064U, // MSUBR_H_rrr1_UU
|
|
2200966064U, // MSUBR_H_rrr1_v110
|
|
3274708446U, // MSUBR_Q_rrr1_L_L
|
|
3543143902U, // MSUBR_Q_rrr1_U_U
|
|
2200966622U, // MSUBR_Q_rrr1_v110
|
|
2200966119U, // MSUBS_H_rrr1_LL
|
|
2200966119U, // MSUBS_H_rrr1_LU
|
|
2200966119U, // MSUBS_H_rrr1_UL
|
|
2200966119U, // MSUBS_H_rrr1_UU
|
|
2200966119U, // MSUBS_H_rrr1_v110
|
|
2200966648U, // MSUBS_Q_rrr1
|
|
2200966648U, // MSUBS_Q_rrr1_L
|
|
3274708472U, // MSUBS_Q_rrr1_L_L
|
|
2200966648U, // MSUBS_Q_rrr1_U
|
|
2200966648U, // MSUBS_Q_rrr1_UU2_v110
|
|
3543143928U, // MSUBS_Q_rrr1_U_U
|
|
2200966648U, // MSUBS_Q_rrr1_e
|
|
2200966648U, // MSUBS_Q_rrr1_e_L
|
|
3274708472U, // MSUBS_Q_rrr1_e_L_L
|
|
2200966648U, // MSUBS_Q_rrr1_e_U
|
|
3543143928U, // MSUBS_Q_rrr1_e_U_U
|
|
1074796593U, // MSUBS_U_rcr
|
|
1074796593U, // MSUBS_U_rcr_e
|
|
2200967217U, // MSUBS_U_rrr2
|
|
2200967217U, // MSUBS_U_rrr2_e
|
|
1074796143U, // MSUBS_rcr
|
|
1074796143U, // MSUBS_rcr_e
|
|
2200966767U, // MSUBS_rrr2
|
|
2200966767U, // MSUBS_rrr2_e
|
|
2200965853U, // MSUB_F_rrr
|
|
2200965941U, // MSUB_H_rrr1_LL
|
|
2200965941U, // MSUB_H_rrr1_LU
|
|
2200965941U, // MSUB_H_rrr1_UL
|
|
2200965941U, // MSUB_H_rrr1_UU
|
|
2200965941U, // MSUB_H_rrr1_v110
|
|
2200966575U, // MSUB_Q_rrr1
|
|
2200966575U, // MSUB_Q_rrr1_L
|
|
3274708399U, // MSUB_Q_rrr1_L_L
|
|
2200966575U, // MSUB_Q_rrr1_U
|
|
2200966575U, // MSUB_Q_rrr1_UU2_v110
|
|
3543143855U, // MSUB_Q_rrr1_U_U
|
|
2200966575U, // MSUB_Q_rrr1_e
|
|
2200966575U, // MSUB_Q_rrr1_e_L
|
|
3274708399U, // MSUB_Q_rrr1_e_L_L
|
|
2200966575U, // MSUB_Q_rrr1_e_U
|
|
3543143855U, // MSUB_Q_rrr1_e_U_U
|
|
1074796480U, // MSUB_U_rcr
|
|
2200967104U, // MSUB_U_rrr2
|
|
1074795087U, // MSUB_rcr
|
|
1074795087U, // MSUB_rcr_e
|
|
2200965711U, // MSUB_rrr2
|
|
2200965711U, // MSUB_rrr2_e
|
|
46662U, // MTCR_rlc
|
|
5174U, // MULMS_H_rr1_LL2e
|
|
5174U, // MULMS_H_rr1_LU2e
|
|
5174U, // MULMS_H_rr1_UL2e
|
|
5174U, // MULMS_H_rr1_UU2e
|
|
5001U, // MULM_H_rr1_LL2e
|
|
5001U, // MULM_H_rr1_LU2e
|
|
5001U, // MULM_H_rr1_UL2e
|
|
5001U, // MULM_H_rr1_UU2e
|
|
268441605U, // MULM_U_rc
|
|
6149U, // MULM_U_rr
|
|
268440913U, // MULM_rc
|
|
5457U, // MULM_rr
|
|
5069U, // MULR_H_rr1_LL2e
|
|
5069U, // MULR_H_rr1_LU2e
|
|
5069U, // MULR_H_rr1_UL2e
|
|
5069U, // MULR_H_rr1_UU2e
|
|
5069U, // MULR_H_rr_v110
|
|
167777776U, // MULR_Q_rr1_2LL
|
|
184554992U, // MULR_Q_rr1_2UU
|
|
5616U, // MULR_Q_rr_v110
|
|
268441658U, // MULS_U_rc
|
|
6202U, // MULS_U_rr2
|
|
6202U, // MULS_U_rr_v110
|
|
268441234U, // MULS_rc
|
|
5778U, // MULS_rr2
|
|
5778U, // MULS_rr_v110
|
|
4854U, // MUL_F_rrr
|
|
4965U, // MUL_H_rr1_LL2e
|
|
4965U, // MUL_H_rr1_LU2e
|
|
4965U, // MUL_H_rr1_UL2e
|
|
4965U, // MUL_H_rr1_UU2e
|
|
4965U, // MUL_H_rr_v110
|
|
5573U, // MUL_Q_rr1_2
|
|
167777733U, // MUL_Q_rr1_2LL
|
|
184554949U, // MUL_Q_rr1_2UU
|
|
5573U, // MUL_Q_rr1_2_L
|
|
5573U, // MUL_Q_rr1_2_Le
|
|
5573U, // MUL_Q_rr1_2_U
|
|
5573U, // MUL_Q_rr1_2_Ue
|
|
5573U, // MUL_Q_rr1_2__e
|
|
5573U, // MUL_Q_rr_v110
|
|
268441580U, // MUL_U_rc
|
|
6124U, // MUL_U_rr2
|
|
268440894U, // MUL_rc
|
|
268440894U, // MUL_rc_e
|
|
5438U, // MUL_rr2
|
|
5438U, // MUL_rr2_e
|
|
5438U, // MUL_rr_v110
|
|
16782654U, // MUL_srr
|
|
1879054032U, // NAND_T
|
|
268440204U, // NAND_rc
|
|
4748U, // NAND_rr
|
|
16781635U, // NEZ_A
|
|
4329U, // NE_A
|
|
268440268U, // NE_rc
|
|
4812U, // NE_rr
|
|
3368U, // NOP_sr
|
|
3368U, // NOP_sys
|
|
1879054124U, // NOR_T
|
|
268441165U, // NOR_rc
|
|
5709U, // NOR_rr
|
|
136781U, // NOR_sr
|
|
136781U, // NOR_sr_v110
|
|
137132U, // NOT_sr_v162
|
|
1879054077U, // ORN_T
|
|
268440951U, // ORN_rc
|
|
5495U, // ORN_rr
|
|
1879054063U, // OR_ANDN_T
|
|
1879054019U, // OR_AND_T
|
|
268441140U, // OR_EQ_rc
|
|
5684U, // OR_EQ_rr
|
|
268441564U, // OR_GE_U_rc
|
|
6108U, // OR_GE_U_rr
|
|
268440226U, // OR_GE_rc
|
|
4770U, // OR_GE_rr
|
|
268441716U, // OR_LT_U_rc
|
|
6260U, // OR_LT_U_rr
|
|
268441504U, // OR_LT_rc
|
|
6048U, // OR_LT_rr
|
|
268440273U, // OR_NE_rc
|
|
4817U, // OR_NE_rr
|
|
1879054141U, // OR_NOR_T
|
|
1879054111U, // OR_OR_T
|
|
1879054096U, // OR_T
|
|
3758102094U, // OR_rc
|
|
5710U, // OR_rr
|
|
139320U, // OR_sc
|
|
139320U, // OR_sc_v110
|
|
16782926U, // OR_srr
|
|
16782926U, // OR_srr_v110
|
|
1664095505U, // PACK_rrr
|
|
16783800U, // PARITY_rr
|
|
16783800U, // PARITY_rr_v110
|
|
16783737U, // POPCNT_W_rr
|
|
4883U, // Q31TOF_rr
|
|
16782061U, // QSEED_F_rr
|
|
3330U, // RESTORE_sys
|
|
3373U, // RET_sr
|
|
3373U, // RET_sys
|
|
3373U, // RET_sys_v110
|
|
3311U, // RFE_sr
|
|
3311U, // RFE_sys_sys
|
|
3311U, // RFE_sys_sys_v110
|
|
3364U, // RFM_sys
|
|
3344U, // RSLCX_sys
|
|
3395U, // RSTV_sys
|
|
268441640U, // RSUBS_U_rc
|
|
268441206U, // RSUBS_rc
|
|
268440149U, // RSUB_rc
|
|
135765U, // RSUB_sr_sr
|
|
135765U, // RSUB_sr_sr_v110
|
|
16783548U, // SAT_BU_rr
|
|
137404U, // SAT_BU_sr
|
|
137404U, // SAT_BU_sr_v110
|
|
16781845U, // SAT_B_rr
|
|
135701U, // SAT_B_sr
|
|
135701U, // SAT_B_sr_v110
|
|
16783615U, // SAT_HU_rr
|
|
137471U, // SAT_HU_sr
|
|
137471U, // SAT_HU_sr_v110
|
|
16782474U, // SAT_H_rr
|
|
136330U, // SAT_H_sr
|
|
136330U, // SAT_H_sr_v110
|
|
1074794777U, // SELN_A_rcr_v110
|
|
2200965401U, // SELN_A_rrr_v110
|
|
1074795889U, // SELN_rcr
|
|
2200966513U, // SELN_rrr
|
|
1074794752U, // SEL_A_rcr_v110
|
|
2200965376U, // SEL_A_rrr_v110
|
|
1074795806U, // SEL_rcr
|
|
2200966430U, // SEL_rrr
|
|
268441188U, // SHAS_rc
|
|
5732U, // SHAS_rr
|
|
268439973U, // SHA_B_rc
|
|
4517U, // SHA_B_rr
|
|
268440366U, // SHA_H_rc
|
|
4910U, // SHA_H_rr
|
|
268439942U, // SHA_rc
|
|
4486U, // SHA_rr
|
|
18878854U, // SHA_src
|
|
18878854U, // SHA_src_v110
|
|
268440255U, // SHUFFLE_rc
|
|
1879054052U, // SH_ANDN_T
|
|
1879054009U, // SH_AND_T
|
|
268440010U, // SH_B_rc
|
|
4554U, // SH_B_rr
|
|
268441132U, // SH_EQ_rc
|
|
5676U, // SH_EQ_rr
|
|
268441554U, // SH_GE_U_rc
|
|
6098U, // SH_GE_U_rr
|
|
268440218U, // SH_GE_rc
|
|
4762U, // SH_GE_rr
|
|
268440415U, // SH_H_rc
|
|
4959U, // SH_H_rr
|
|
268441706U, // SH_LT_U_rc
|
|
6250U, // SH_LT_U_rr
|
|
268441496U, // SH_LT_rc
|
|
6040U, // SH_LT_rr
|
|
1879054029U, // SH_NAND_T
|
|
268441496U, // SH_NE_rc
|
|
6040U, // SH_NE_rr
|
|
1879054131U, // SH_NOR_T
|
|
1879054074U, // SH_ORN_T
|
|
1879054102U, // SH_OR_T
|
|
1879054151U, // SH_XNOR_T
|
|
1879054162U, // SH_XOR_T
|
|
268440783U, // SH_rc
|
|
5327U, // SH_rr
|
|
18879695U, // SH_src
|
|
18879695U, // SH_src_v110
|
|
166301U, // STLCX_abs
|
|
4398157U, // STLCX_bo_bso
|
|
166315U, // STUCX_abs
|
|
4398173U, // STUCX_bo_bso
|
|
37174U, // ST_A_abs
|
|
72575919U, // ST_A_bo_bso
|
|
117969206U, // ST_A_bo_c
|
|
3093848374U, // ST_A_bo_pos
|
|
3060359478U, // ST_A_bo_pre
|
|
151523638U, // ST_A_bo_r
|
|
13835183U, // ST_A_bol
|
|
732343U, // ST_A_sc
|
|
209918895U, // ST_A_sro
|
|
209918895U, // ST_A_sro_v110
|
|
793519U, // ST_A_ssr
|
|
859055U, // ST_A_ssr_pos
|
|
859055U, // ST_A_ssr_pos_v110
|
|
793519U, // ST_A_ssr_v110
|
|
52325U, // ST_A_ssro
|
|
52325U, // ST_A_ssro_v110
|
|
37420U, // ST_B_abs
|
|
72575934U, // ST_B_bo_bso
|
|
117969452U, // ST_B_bo_c
|
|
3093848620U, // ST_B_bo_pos
|
|
3060359724U, // ST_B_bo_pre
|
|
151523884U, // ST_B_bo_r
|
|
13835198U, // ST_B_bol
|
|
226696126U, // ST_B_sro
|
|
226696126U, // ST_B_sro_v110
|
|
793534U, // ST_B_ssr
|
|
859070U, // ST_B_ssr_pos
|
|
859070U, // ST_B_ssr_pos_v110
|
|
793534U, // ST_B_ssr_v110
|
|
52337U, // ST_B_ssro
|
|
52337U, // ST_B_ssro_v110
|
|
37237U, // ST_DA_abs
|
|
72575926U, // ST_DA_bo_bso
|
|
117969269U, // ST_DA_bo_c
|
|
3093848437U, // ST_DA_bo_pos
|
|
3060359541U, // ST_DA_bo_pre
|
|
151523701U, // ST_DA_bo_r
|
|
37485U, // ST_D_abs
|
|
72575941U, // ST_D_bo_bso
|
|
117969517U, // ST_D_bo_c
|
|
3093848685U, // ST_D_bo_pos
|
|
3060359789U, // ST_D_bo_pre
|
|
151523949U, // ST_D_bo_r
|
|
38049U, // ST_H_abs
|
|
72575948U, // ST_H_bo_bso
|
|
117970081U, // ST_H_bo_c
|
|
3093849249U, // ST_H_bo_pos
|
|
3060360353U, // ST_H_bo_pre
|
|
151524513U, // ST_H_bo_r
|
|
13835212U, // ST_H_bol
|
|
226696140U, // ST_H_sro
|
|
226696140U, // ST_H_sro_v110
|
|
793548U, // ST_H_ssr
|
|
859084U, // ST_H_ssr_pos
|
|
859084U, // ST_H_ssr_pos_v110
|
|
793548U, // ST_H_ssr_v110
|
|
52349U, // ST_H_ssro
|
|
52349U, // ST_H_ssro_v110
|
|
38430U, // ST_Q_abs
|
|
72576001U, // ST_Q_bo_bso
|
|
117970462U, // ST_Q_bo_c
|
|
3093849630U, // ST_Q_bo_pos
|
|
3060360734U, // ST_Q_bo_pre
|
|
151524894U, // ST_Q_bo_r
|
|
34659U, // ST_T
|
|
39299U, // ST_W_abs
|
|
72576062U, // ST_W_bo_bso
|
|
117971331U, // ST_W_bo_c
|
|
3093850499U, // ST_W_bo_pos
|
|
3060361603U, // ST_W_bo_pre
|
|
151525763U, // ST_W_bo_r
|
|
13835326U, // ST_W_bol
|
|
928962U, // ST_W_sc
|
|
226696254U, // ST_W_sro
|
|
226696254U, // ST_W_sro_v110
|
|
793662U, // ST_W_ssr
|
|
859198U, // ST_W_ssr_pos
|
|
859198U, // ST_W_ssr_pos_v110
|
|
793662U, // ST_W_ssr_v110
|
|
52361U, // ST_W_ssro
|
|
52361U, // ST_W_ssro_v110
|
|
4699U, // SUBC_rr
|
|
4269U, // SUBSC_A_rr
|
|
6314U, // SUBS_BU_rr
|
|
4587U, // SUBS_B_rr
|
|
6381U, // SUBS_HU_rr
|
|
5096U, // SUBS_H_rr
|
|
6185U, // SUBS_U_rr
|
|
5744U, // SUBS_rr
|
|
16782960U, // SUBS_srr
|
|
6544U, // SUBX_rr
|
|
4262U, // SUB_A_rr
|
|
139409U, // SUB_A_sc
|
|
139409U, // SUB_A_sc_v110
|
|
4524U, // SUB_B_rr
|
|
1664094942U, // SUB_F_rrr
|
|
4918U, // SUB_H_rr
|
|
4682U, // SUB_rr
|
|
16781898U, // SUB_srr
|
|
16781313U, // SUB_srr_15a
|
|
16847434U, // SUB_srr_a15
|
|
3400U, // SVLCX_sys
|
|
72576038U, // SWAPMSK_W_bo_bso
|
|
117971280U, // SWAPMSK_W_bo_c
|
|
3093850448U, // SWAPMSK_W_bo_pos
|
|
3060361552U, // SWAPMSK_W_bo_pre
|
|
151525712U, // SWAPMSK_W_bo_r
|
|
37153U, // SWAP_A_abs
|
|
72575910U, // SWAP_A_bo_bso
|
|
1666456486U, // SWAP_A_bo_c
|
|
72706982U, // SWAP_A_bo_pos
|
|
72575485U, // SWAP_A_bo_pre
|
|
17243046U, // SWAP_A_bo_r
|
|
39269U, // SWAP_W_abs
|
|
72576053U, // SWAP_W_bo_bso
|
|
1666456629U, // SWAP_W_bo_c
|
|
1010741U, // SWAP_W_bo_indexed
|
|
72707125U, // SWAP_W_bo_pos
|
|
72575581U, // SWAP_W_bo_pre
|
|
17243189U, // SWAP_W_bo_r
|
|
13621U, // SYSCALL_rc
|
|
136592U, // TLBDEMAP_rr
|
|
3277U, // TLBFLUSH_A_rr
|
|
3288U, // TLBFLUSH_B_rr
|
|
136584U, // TLBMAP_rr
|
|
135382U, // TLBPROBE_A_rr
|
|
136409U, // TLBPROBE_I_rr
|
|
3388U, // TRAPSV_sys
|
|
3382U, // TRAPV_sys
|
|
16782607U, // UNPACK_rr_rr
|
|
16782607U, // UNPACK_rr_rr_v110
|
|
136483U, // UPDFL_rr
|
|
16782120U, // UTOF_rr
|
|
3377U, // WAIT_sys
|
|
1879054154U, // XNOR_T
|
|
268441164U, // XNOR_rc
|
|
5708U, // XNOR_rr
|
|
268441139U, // XOR_EQ_rc
|
|
5683U, // XOR_EQ_rr
|
|
268441563U, // XOR_GE_U_rc
|
|
6107U, // XOR_GE_U_rr
|
|
268440225U, // XOR_GE_rc
|
|
4769U, // XOR_GE_rr
|
|
268441715U, // XOR_LT_U_rc
|
|
6259U, // XOR_LT_U_rr
|
|
268441503U, // XOR_LT_rc
|
|
6047U, // XOR_LT_rr
|
|
268440272U, // XOR_NE_rc
|
|
4816U, // XOR_NE_rr
|
|
1879054165U, // XOR_T
|
|
268441170U, // XOR_rc
|
|
5714U, // XOR_rr
|
|
16782930U, // XOR_srr
|
|
};
|
|
|
|
static const uint8_t OpInfo1[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
0U, // DBG_VALUE
|
|
0U, // DBG_VALUE_LIST
|
|
0U, // DBG_INSTR_REF
|
|
0U, // DBG_PHI
|
|
0U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
0U, // BUNDLE
|
|
0U, // LIFETIME_START
|
|
0U, // LIFETIME_END
|
|
0U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
0U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
0U, // PATCHABLE_FUNCTION_ENTER
|
|
0U, // PATCHABLE_RET
|
|
0U, // PATCHABLE_FUNCTION_EXIT
|
|
0U, // PATCHABLE_TAIL_CALL
|
|
0U, // PATCHABLE_EVENT_CALL
|
|
0U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_INTRINSIC_FPTRUNC_ROUND
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_ATOMICRMW_FMAX
|
|
0U, // G_ATOMICRMW_FMIN
|
|
0U, // G_FENCE
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INVOKE_REGION_START
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_IS_FPCLASS
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
0U, // ABSDIFS_B_rr_v110
|
|
0U, // ABSDIFS_H_rr
|
|
0U, // ABSDIFS_rc
|
|
0U, // ABSDIFS_rr
|
|
0U, // ABSDIF_B_rr
|
|
0U, // ABSDIF_H_rr
|
|
0U, // ABSDIF_rc
|
|
0U, // ABSDIF_rr
|
|
0U, // ABSS_B_rr_v110
|
|
0U, // ABSS_H_rr
|
|
0U, // ABSS_rr
|
|
0U, // ABS_B_rr
|
|
0U, // ABS_H_rr
|
|
0U, // ABS_rr
|
|
0U, // ADDC_rc
|
|
0U, // ADDC_rr
|
|
0U, // ADDIH_A_rlc
|
|
0U, // ADDIH_rlc
|
|
0U, // ADDI_rlc
|
|
0U, // ADDSC_AT_rr
|
|
0U, // ADDSC_AT_rr_v110
|
|
1U, // ADDSC_A_rr
|
|
1U, // ADDSC_A_rr_v110
|
|
0U, // ADDSC_A_srrs
|
|
0U, // ADDSC_A_srrs_v110
|
|
0U, // ADDS_BU_rr_v110
|
|
0U, // ADDS_B_rr_v110
|
|
0U, // ADDS_H
|
|
0U, // ADDS_HU
|
|
0U, // ADDS_U
|
|
0U, // ADDS_U_rc
|
|
0U, // ADDS_rc
|
|
0U, // ADDS_rr
|
|
0U, // ADDS_srr
|
|
0U, // ADDX_rc
|
|
0U, // ADDX_rr
|
|
0U, // ADD_A_rr
|
|
0U, // ADD_A_src
|
|
0U, // ADD_A_srr
|
|
0U, // ADD_B_rr
|
|
0U, // ADD_F_rrr
|
|
0U, // ADD_H_rr
|
|
0U, // ADD_rc
|
|
0U, // ADD_rr
|
|
0U, // ADD_src
|
|
0U, // ADD_src_15a
|
|
0U, // ADD_src_a15
|
|
0U, // ADD_srr
|
|
0U, // ADD_srr_15a
|
|
0U, // ADD_srr_a15
|
|
0U, // ANDN_T
|
|
0U, // ANDN_rc
|
|
0U, // ANDN_rr
|
|
0U, // AND_ANDN_T
|
|
0U, // AND_AND_T
|
|
0U, // AND_EQ_rc
|
|
0U, // AND_EQ_rr
|
|
0U, // AND_GE_U_rc
|
|
0U, // AND_GE_U_rr
|
|
0U, // AND_GE_rc
|
|
0U, // AND_GE_rr
|
|
0U, // AND_LT_U_rc
|
|
0U, // AND_LT_U_rr
|
|
0U, // AND_LT_rc
|
|
0U, // AND_LT_rr
|
|
0U, // AND_NE_rc
|
|
0U, // AND_NE_rr
|
|
0U, // AND_NOR_T
|
|
0U, // AND_OR_T
|
|
0U, // AND_T
|
|
0U, // AND_rc
|
|
0U, // AND_rr
|
|
0U, // AND_sc
|
|
0U, // AND_sc_v110
|
|
0U, // AND_srr
|
|
0U, // AND_srr_v110
|
|
0U, // BISR_rc
|
|
0U, // BISR_rc_v161
|
|
0U, // BISR_sc
|
|
0U, // BISR_sc_v110
|
|
0U, // BMERGAE_rr_v110
|
|
0U, // BMERGE_rr
|
|
0U, // BSPLIT_rr
|
|
0U, // BSPLIT_rr_v110
|
|
0U, // CACHEA_I_bo_bso
|
|
0U, // CACHEA_I_bo_c
|
|
0U, // CACHEA_I_bo_pos
|
|
0U, // CACHEA_I_bo_pre
|
|
0U, // CACHEA_I_bo_r
|
|
0U, // CACHEA_WI_bo_bso
|
|
0U, // CACHEA_WI_bo_c
|
|
0U, // CACHEA_WI_bo_pos
|
|
0U, // CACHEA_WI_bo_pre
|
|
0U, // CACHEA_WI_bo_r
|
|
0U, // CACHEA_W_bo_bso
|
|
0U, // CACHEA_W_bo_c
|
|
0U, // CACHEA_W_bo_pos
|
|
0U, // CACHEA_W_bo_pre
|
|
0U, // CACHEA_W_bo_r
|
|
0U, // CACHEI_I_bo_bso
|
|
0U, // CACHEI_I_bo_pos
|
|
0U, // CACHEI_I_bo_pre
|
|
0U, // CACHEI_WI_bo_bso
|
|
0U, // CACHEI_WI_bo_pos
|
|
0U, // CACHEI_WI_bo_pre
|
|
0U, // CACHEI_W_bo_bso
|
|
0U, // CACHEI_W_bo_pos
|
|
0U, // CACHEI_W_bo_pre
|
|
17U, // CADDN_A_rcr_v110
|
|
0U, // CADDN_A_rrr_v110
|
|
17U, // CADDN_rcr
|
|
0U, // CADDN_rrr
|
|
0U, // CADDN_src
|
|
0U, // CADDN_srr_v110
|
|
17U, // CADD_A_rcr_v110
|
|
0U, // CADD_A_rrr_v110
|
|
17U, // CADD_rcr
|
|
0U, // CADD_rrr
|
|
0U, // CADD_src
|
|
0U, // CADD_srr_v110
|
|
0U, // CALLA_b
|
|
0U, // CALLI_rr
|
|
0U, // CALLI_rr_v110
|
|
0U, // CALL_b
|
|
0U, // CALL_sb
|
|
0U, // CLO_B_rr_v110
|
|
0U, // CLO_H_rr
|
|
0U, // CLO_rr
|
|
0U, // CLS_B_rr_v110
|
|
0U, // CLS_H_rr
|
|
0U, // CLS_rr
|
|
0U, // CLZ_B_rr_v110
|
|
0U, // CLZ_H_rr
|
|
0U, // CLZ_rr
|
|
0U, // CMOVN_src
|
|
0U, // CMOVN_srr
|
|
0U, // CMOV_src
|
|
0U, // CMOV_srr
|
|
0U, // CMPSWAP_W_bo_bso
|
|
0U, // CMPSWAP_W_bo_c
|
|
0U, // CMPSWAP_W_bo_pos
|
|
0U, // CMPSWAP_W_bo_pre
|
|
0U, // CMPSWAP_W_bo_r
|
|
0U, // CMP_F_rr
|
|
0U, // CRC32B_W_rr
|
|
0U, // CRC32L_W_rr
|
|
0U, // CRC32_B_rr
|
|
0U, // CRCN_rrr
|
|
0U, // CSUBN_A__rrr_v110
|
|
0U, // CSUBN_rrr
|
|
0U, // CSUB_A__rrr_v110
|
|
0U, // CSUB_rrr
|
|
0U, // DEBUG_sr
|
|
0U, // DEBUG_sys
|
|
33U, // DEXTR_rrpw
|
|
33U, // DEXTR_rrrr
|
|
1U, // DIFSC_A_rr_v110
|
|
0U, // DISABLE_sys
|
|
0U, // DISABLE_sys_1
|
|
0U, // DIV_F_rr
|
|
0U, // DIV_U_rr
|
|
0U, // DIV_rr
|
|
0U, // DSYNC_sys
|
|
0U, // DVADJ_rrr
|
|
0U, // DVADJ_rrr_v110
|
|
0U, // DVADJ_srr_v110
|
|
0U, // DVINIT_BU_rr
|
|
0U, // DVINIT_BU_rr_v110
|
|
0U, // DVINIT_B_rr
|
|
0U, // DVINIT_B_rr_v110
|
|
0U, // DVINIT_HU_rr
|
|
0U, // DVINIT_HU_rr_v110
|
|
0U, // DVINIT_H_rr
|
|
0U, // DVINIT_H_rr_v110
|
|
0U, // DVINIT_U_rr
|
|
0U, // DVINIT_U_rr_v110
|
|
0U, // DVINIT_rr
|
|
0U, // DVINIT_rr_v110
|
|
0U, // DVSTEP_U_rrr
|
|
0U, // DVSTEP_U_rrrv110
|
|
0U, // DVSTEP_Uv110
|
|
0U, // DVSTEP_rrr
|
|
0U, // DVSTEP_rrrv110
|
|
0U, // DVSTEPv110
|
|
0U, // ENABLE_sys
|
|
0U, // EQANY_B_rc
|
|
0U, // EQANY_B_rr
|
|
0U, // EQANY_H_rc
|
|
0U, // EQANY_H_rr
|
|
0U, // EQZ_A_rr
|
|
0U, // EQ_A_rr
|
|
0U, // EQ_B_rr
|
|
0U, // EQ_H_rr
|
|
0U, // EQ_W_rr
|
|
0U, // EQ_rc
|
|
0U, // EQ_rr
|
|
0U, // EQ_src
|
|
0U, // EQ_srr
|
|
33U, // EXTR_U_rrpw
|
|
0U, // EXTR_U_rrrr
|
|
2U, // EXTR_U_rrrw
|
|
33U, // EXTR_rrpw
|
|
0U, // EXTR_rrrr
|
|
2U, // EXTR_rrrw
|
|
0U, // FCALLA_b
|
|
0U, // FCALLA_i
|
|
0U, // FCALL_b
|
|
0U, // FRET_sr
|
|
0U, // FRET_sys
|
|
0U, // FTOHP_rr
|
|
0U, // FTOIZ_rr
|
|
0U, // FTOI_rr
|
|
0U, // FTOQ31Z_rr
|
|
0U, // FTOQ31_rr
|
|
0U, // FTOUZ_rr
|
|
0U, // FTOU_rr
|
|
0U, // GE_A_rr
|
|
0U, // GE_U_rc
|
|
0U, // GE_U_rr
|
|
0U, // GE_rc
|
|
0U, // GE_rr
|
|
0U, // HPTOF_rr
|
|
33U, // IMASK_rcpw
|
|
33U, // IMASK_rcrw
|
|
33U, // IMASK_rrpw
|
|
2U, // IMASK_rrrw
|
|
161U, // INSERT_rcpw
|
|
33U, // INSERT_rcrr
|
|
3U, // INSERT_rcrw
|
|
161U, // INSERT_rrpw
|
|
161U, // INSERT_rrrr
|
|
161U, // INSERT_rrrw
|
|
0U, // INSN_T
|
|
0U, // INS_T
|
|
0U, // ISYNC_sys
|
|
0U, // ITOF_rr
|
|
0U, // IXMAX_U_rrr
|
|
0U, // IXMAX_rrr
|
|
0U, // IXMIN_U_rrr
|
|
0U, // IXMIN_rrr
|
|
0U, // JA_b
|
|
0U, // JEQ_A_brr
|
|
0U, // JEQ_brc
|
|
0U, // JEQ_brr
|
|
0U, // JEQ_sbc1
|
|
0U, // JEQ_sbc2
|
|
0U, // JEQ_sbc_v110
|
|
0U, // JEQ_sbr1
|
|
0U, // JEQ_sbr2
|
|
0U, // JEQ_sbr_v110
|
|
0U, // JGEZ_sbr
|
|
0U, // JGEZ_sbr_v110
|
|
0U, // JGE_U_brc
|
|
0U, // JGE_U_brr
|
|
0U, // JGE_brc
|
|
0U, // JGE_brr
|
|
0U, // JGTZ_sbr
|
|
0U, // JGTZ_sbr_v110
|
|
0U, // JI_rr
|
|
0U, // JI_rr_v110
|
|
0U, // JI_sbr_v110
|
|
0U, // JI_sr
|
|
0U, // JLA_b
|
|
0U, // JLEZ_sbr
|
|
0U, // JLEZ_sbr_v110
|
|
0U, // JLI_rr
|
|
0U, // JLI_rr_v110
|
|
0U, // JLTZ_sbr
|
|
0U, // JLTZ_sbr_v110
|
|
0U, // JLT_U_brc
|
|
0U, // JLT_U_brr
|
|
0U, // JLT_brc
|
|
0U, // JLT_brr
|
|
0U, // JL_b
|
|
0U, // JNED_brc
|
|
0U, // JNED_brr
|
|
0U, // JNEI_brc
|
|
0U, // JNEI_brr
|
|
0U, // JNE_A_brr
|
|
0U, // JNE_brc
|
|
0U, // JNE_brr
|
|
0U, // JNE_sbc1
|
|
0U, // JNE_sbc2
|
|
0U, // JNE_sbc_v110
|
|
0U, // JNE_sbr1
|
|
0U, // JNE_sbr2
|
|
0U, // JNE_sbr_v110
|
|
0U, // JNZ_A_brr
|
|
0U, // JNZ_A_sbr
|
|
0U, // JNZ_T_brn
|
|
0U, // JNZ_T_sbrn
|
|
0U, // JNZ_T_sbrn_v110
|
|
0U, // JNZ_sb
|
|
0U, // JNZ_sb_v110
|
|
0U, // JNZ_sbr
|
|
0U, // JNZ_sbr_v110
|
|
0U, // JZ_A_brr
|
|
0U, // JZ_A_sbr
|
|
0U, // JZ_T_brn
|
|
0U, // JZ_T_sbrn
|
|
0U, // JZ_T_sbrn_v110
|
|
0U, // JZ_sb
|
|
0U, // JZ_sb_v110
|
|
0U, // JZ_sbr
|
|
0U, // JZ_sbr_v110
|
|
0U, // J_b
|
|
0U, // J_sb
|
|
0U, // J_sb_v110
|
|
0U, // LDLCX_abs
|
|
0U, // LDLCX_bo_bso
|
|
0U, // LDMST_abs
|
|
0U, // LDMST_bo_bso
|
|
0U, // LDMST_bo_c
|
|
0U, // LDMST_bo_pos
|
|
0U, // LDMST_bo_pre
|
|
0U, // LDMST_bo_r
|
|
0U, // LDUCX_abs
|
|
0U, // LDUCX_bo_bso
|
|
0U, // LD_A_abs
|
|
0U, // LD_A_bo_bso
|
|
0U, // LD_A_bo_c
|
|
0U, // LD_A_bo_pos
|
|
0U, // LD_A_bo_pre
|
|
0U, // LD_A_bo_r
|
|
0U, // LD_A_bol
|
|
0U, // LD_A_sc
|
|
0U, // LD_A_slr
|
|
0U, // LD_A_slr_post
|
|
0U, // LD_A_slr_post_v110
|
|
0U, // LD_A_slr_v110
|
|
0U, // LD_A_slro
|
|
0U, // LD_A_slro_v110
|
|
0U, // LD_A_sro
|
|
0U, // LD_A_sro_v110
|
|
0U, // LD_BU_abs
|
|
0U, // LD_BU_bo_bso
|
|
0U, // LD_BU_bo_c
|
|
0U, // LD_BU_bo_pos
|
|
0U, // LD_BU_bo_pre
|
|
0U, // LD_BU_bo_r
|
|
0U, // LD_BU_bol
|
|
0U, // LD_BU_slr
|
|
0U, // LD_BU_slr_post
|
|
0U, // LD_BU_slr_post_v110
|
|
0U, // LD_BU_slr_v110
|
|
0U, // LD_BU_slro
|
|
0U, // LD_BU_slro_v110
|
|
0U, // LD_BU_sro
|
|
0U, // LD_BU_sro_v110
|
|
0U, // LD_B_abs
|
|
0U, // LD_B_bo_bso
|
|
0U, // LD_B_bo_c
|
|
0U, // LD_B_bo_pos
|
|
0U, // LD_B_bo_pre
|
|
0U, // LD_B_bo_r
|
|
0U, // LD_B_bol
|
|
0U, // LD_B_slr_post_v110
|
|
0U, // LD_B_slr_v110
|
|
0U, // LD_B_slro_v110
|
|
0U, // LD_B_sro_v110
|
|
0U, // LD_DA_abs
|
|
0U, // LD_DA_bo_bso
|
|
0U, // LD_DA_bo_c
|
|
0U, // LD_DA_bo_pos
|
|
0U, // LD_DA_bo_pre
|
|
0U, // LD_DA_bo_r
|
|
0U, // LD_D_abs
|
|
0U, // LD_D_bo_bso
|
|
0U, // LD_D_bo_c
|
|
0U, // LD_D_bo_pos
|
|
0U, // LD_D_bo_pre
|
|
0U, // LD_D_bo_r
|
|
0U, // LD_HU_abs
|
|
0U, // LD_HU_bo_bso
|
|
0U, // LD_HU_bo_c
|
|
0U, // LD_HU_bo_pos
|
|
0U, // LD_HU_bo_pre
|
|
0U, // LD_HU_bo_r
|
|
0U, // LD_HU_bol
|
|
0U, // LD_H_abs
|
|
0U, // LD_H_bo_bso
|
|
0U, // LD_H_bo_c
|
|
0U, // LD_H_bo_pos
|
|
0U, // LD_H_bo_pre
|
|
0U, // LD_H_bo_r
|
|
0U, // LD_H_bol
|
|
0U, // LD_H_slr
|
|
0U, // LD_H_slr_post
|
|
0U, // LD_H_slr_post_v110
|
|
0U, // LD_H_slr_v110
|
|
0U, // LD_H_slro
|
|
0U, // LD_H_slro_v110
|
|
0U, // LD_H_sro
|
|
0U, // LD_H_sro_v110
|
|
0U, // LD_Q_abs
|
|
0U, // LD_Q_bo_bso
|
|
0U, // LD_Q_bo_c
|
|
0U, // LD_Q_bo_pos
|
|
0U, // LD_Q_bo_pre
|
|
0U, // LD_Q_bo_r
|
|
0U, // LD_W_abs
|
|
0U, // LD_W_bo_bso
|
|
0U, // LD_W_bo_c
|
|
0U, // LD_W_bo_pos
|
|
0U, // LD_W_bo_pre
|
|
0U, // LD_W_bo_r
|
|
0U, // LD_W_bol
|
|
0U, // LD_W_sc
|
|
0U, // LD_W_slr
|
|
0U, // LD_W_slr_post
|
|
0U, // LD_W_slr_post_v110
|
|
0U, // LD_W_slr_v110
|
|
0U, // LD_W_slro
|
|
0U, // LD_W_slro_v110
|
|
0U, // LD_W_sro
|
|
0U, // LD_W_sro_v110
|
|
0U, // LEA_abs
|
|
0U, // LEA_bo_bso
|
|
0U, // LEA_bol
|
|
0U, // LHA_abs
|
|
0U, // LOOPU_brr
|
|
0U, // LOOP_brr
|
|
0U, // LOOP_sbr
|
|
0U, // LT_A_rr
|
|
0U, // LT_B
|
|
0U, // LT_BU
|
|
0U, // LT_H
|
|
0U, // LT_HU
|
|
0U, // LT_U_rc
|
|
0U, // LT_U_rr
|
|
0U, // LT_U_srcv110
|
|
0U, // LT_U_srrv110
|
|
0U, // LT_W
|
|
0U, // LT_WU
|
|
0U, // LT_rc
|
|
0U, // LT_rr
|
|
0U, // LT_src
|
|
0U, // LT_srr
|
|
52U, // MADDMS_H_rrr1_LL
|
|
53U, // MADDMS_H_rrr1_LU
|
|
54U, // MADDMS_H_rrr1_UL
|
|
55U, // MADDMS_H_rrr1_UU
|
|
65U, // MADDMS_U_rcr_v110
|
|
0U, // MADDMS_U_rrr2_v110
|
|
17U, // MADDMS_rcr_v110
|
|
0U, // MADDMS_rrr2_v110
|
|
52U, // MADDM_H_rrr1_LL
|
|
53U, // MADDM_H_rrr1_LU
|
|
54U, // MADDM_H_rrr1_UL
|
|
55U, // MADDM_H_rrr1_UU
|
|
0U, // MADDM_H_rrr1_v110
|
|
0U, // MADDM_Q_rrr1_v110
|
|
65U, // MADDM_U_rcr_v110
|
|
0U, // MADDM_U_rrr2_v110
|
|
17U, // MADDM_rcr_v110
|
|
0U, // MADDM_rrr2_v110
|
|
52U, // MADDRS_H_rrr1_LL
|
|
53U, // MADDRS_H_rrr1_LU
|
|
54U, // MADDRS_H_rrr1_UL
|
|
54U, // MADDRS_H_rrr1_UL_2
|
|
55U, // MADDRS_H_rrr1_UU
|
|
49U, // MADDRS_H_rrr1_v110
|
|
0U, // MADDRS_Q_rrr1_L_L
|
|
0U, // MADDRS_Q_rrr1_U_U
|
|
49U, // MADDRS_Q_rrr1_v110
|
|
52U, // MADDR_H_rrr1_LL
|
|
53U, // MADDR_H_rrr1_LU
|
|
54U, // MADDR_H_rrr1_UL
|
|
54U, // MADDR_H_rrr1_UL_2
|
|
55U, // MADDR_H_rrr1_UU
|
|
49U, // MADDR_H_rrr1_v110
|
|
0U, // MADDR_Q_rrr1_L_L
|
|
0U, // MADDR_Q_rrr1_U_U
|
|
49U, // MADDR_Q_rrr1_v110
|
|
52U, // MADDSUMS_H_rrr1_LL
|
|
53U, // MADDSUMS_H_rrr1_LU
|
|
54U, // MADDSUMS_H_rrr1_UL
|
|
55U, // MADDSUMS_H_rrr1_UU
|
|
52U, // MADDSUM_H_rrr1_LL
|
|
53U, // MADDSUM_H_rrr1_LU
|
|
54U, // MADDSUM_H_rrr1_UL
|
|
55U, // MADDSUM_H_rrr1_UU
|
|
52U, // MADDSURS_H_rrr1_LL
|
|
53U, // MADDSURS_H_rrr1_LU
|
|
54U, // MADDSURS_H_rrr1_UL
|
|
55U, // MADDSURS_H_rrr1_UU
|
|
52U, // MADDSUR_H_rrr1_LL
|
|
53U, // MADDSUR_H_rrr1_LU
|
|
54U, // MADDSUR_H_rrr1_UL
|
|
55U, // MADDSUR_H_rrr1_UU
|
|
52U, // MADDSUS_H_rrr1_LL
|
|
53U, // MADDSUS_H_rrr1_LU
|
|
54U, // MADDSUS_H_rrr1_UL
|
|
55U, // MADDSUS_H_rrr1_UU
|
|
52U, // MADDSU_H_rrr1_LL
|
|
53U, // MADDSU_H_rrr1_LU
|
|
54U, // MADDSU_H_rrr1_UL
|
|
55U, // MADDSU_H_rrr1_UU
|
|
52U, // MADDS_H_rrr1_LL
|
|
53U, // MADDS_H_rrr1_LU
|
|
54U, // MADDS_H_rrr1_UL
|
|
55U, // MADDS_H_rrr1_UU
|
|
49U, // MADDS_H_rrr1_v110
|
|
49U, // MADDS_Q_rrr1
|
|
56U, // MADDS_Q_rrr1_L
|
|
0U, // MADDS_Q_rrr1_L_L
|
|
57U, // MADDS_Q_rrr1_U
|
|
49U, // MADDS_Q_rrr1_UU2_v110
|
|
0U, // MADDS_Q_rrr1_U_U
|
|
49U, // MADDS_Q_rrr1_e
|
|
56U, // MADDS_Q_rrr1_e_L
|
|
0U, // MADDS_Q_rrr1_e_L_L
|
|
57U, // MADDS_Q_rrr1_e_U
|
|
0U, // MADDS_Q_rrr1_e_U_U
|
|
17U, // MADDS_U_rcr
|
|
17U, // MADDS_U_rcr_e
|
|
0U, // MADDS_U_rrr2
|
|
0U, // MADDS_U_rrr2_e
|
|
17U, // MADDS_rcr
|
|
17U, // MADDS_rcr_e
|
|
0U, // MADDS_rrr2
|
|
0U, // MADDS_rrr2_e
|
|
0U, // MADD_F_rrr
|
|
52U, // MADD_H_rrr1_LL
|
|
53U, // MADD_H_rrr1_LU
|
|
54U, // MADD_H_rrr1_UL
|
|
55U, // MADD_H_rrr1_UU
|
|
49U, // MADD_H_rrr1_v110
|
|
49U, // MADD_Q_rrr1
|
|
56U, // MADD_Q_rrr1_L
|
|
0U, // MADD_Q_rrr1_L_L
|
|
57U, // MADD_Q_rrr1_U
|
|
49U, // MADD_Q_rrr1_UU2_v110
|
|
0U, // MADD_Q_rrr1_U_U
|
|
49U, // MADD_Q_rrr1_e
|
|
56U, // MADD_Q_rrr1_e_L
|
|
0U, // MADD_Q_rrr1_e_L_L
|
|
57U, // MADD_Q_rrr1_e_U
|
|
0U, // MADD_Q_rrr1_e_U_U
|
|
65U, // MADD_U_rcr
|
|
0U, // MADD_U_rrr2
|
|
17U, // MADD_rcr
|
|
17U, // MADD_rcr_e
|
|
0U, // MADD_rrr2
|
|
0U, // MADD_rrr2_e
|
|
0U, // MAX_B
|
|
0U, // MAX_BU
|
|
0U, // MAX_H
|
|
0U, // MAX_HU
|
|
0U, // MAX_U_rc
|
|
0U, // MAX_U_rr
|
|
0U, // MAX_rc
|
|
0U, // MAX_rr
|
|
0U, // MFCR_rlc
|
|
0U, // MIN_B
|
|
0U, // MIN_BU
|
|
0U, // MIN_H
|
|
0U, // MIN_HU
|
|
0U, // MIN_U_rc
|
|
0U, // MIN_U_rr
|
|
0U, // MIN_rc
|
|
0U, // MIN_rr
|
|
0U, // MOVH_A_rlc
|
|
0U, // MOVH_rlc
|
|
0U, // MOVZ_A_sr
|
|
0U, // MOV_AA_rr
|
|
0U, // MOV_AA_srr_srr
|
|
0U, // MOV_AA_srr_srr_v110
|
|
0U, // MOV_A_rr
|
|
0U, // MOV_A_src
|
|
0U, // MOV_A_srr
|
|
0U, // MOV_A_srr_v110
|
|
0U, // MOV_D_rr
|
|
0U, // MOV_D_srr_srr
|
|
0U, // MOV_D_srr_srr_v110
|
|
0U, // MOV_U_rlc
|
|
0U, // MOV_rlc
|
|
0U, // MOV_rlc_e
|
|
0U, // MOV_rr
|
|
0U, // MOV_rr_e
|
|
0U, // MOV_rr_eab
|
|
0U, // MOV_sc
|
|
0U, // MOV_sc_v110
|
|
0U, // MOV_src
|
|
0U, // MOV_src_e
|
|
0U, // MOV_srr
|
|
52U, // MSUBADMS_H_rrr1_LL
|
|
53U, // MSUBADMS_H_rrr1_LU
|
|
54U, // MSUBADMS_H_rrr1_UL
|
|
55U, // MSUBADMS_H_rrr1_UU
|
|
52U, // MSUBADM_H_rrr1_LL
|
|
53U, // MSUBADM_H_rrr1_LU
|
|
54U, // MSUBADM_H_rrr1_UL
|
|
55U, // MSUBADM_H_rrr1_UU
|
|
52U, // MSUBADRS_H_rrr1_LL
|
|
53U, // MSUBADRS_H_rrr1_LU
|
|
54U, // MSUBADRS_H_rrr1_UL
|
|
55U, // MSUBADRS_H_rrr1_UU
|
|
49U, // MSUBADRS_H_rrr1_v110
|
|
52U, // MSUBADR_H_rrr1_LL
|
|
53U, // MSUBADR_H_rrr1_LU
|
|
54U, // MSUBADR_H_rrr1_UL
|
|
55U, // MSUBADR_H_rrr1_UU
|
|
49U, // MSUBADR_H_rrr1_v110
|
|
52U, // MSUBADS_H_rrr1_LL
|
|
53U, // MSUBADS_H_rrr1_LU
|
|
54U, // MSUBADS_H_rrr1_UL
|
|
55U, // MSUBADS_H_rrr1_UU
|
|
52U, // MSUBAD_H_rrr1_LL
|
|
53U, // MSUBAD_H_rrr1_LU
|
|
54U, // MSUBAD_H_rrr1_UL
|
|
55U, // MSUBAD_H_rrr1_UU
|
|
52U, // MSUBMS_H_rrr1_LL
|
|
53U, // MSUBMS_H_rrr1_LU
|
|
54U, // MSUBMS_H_rrr1_UL
|
|
55U, // MSUBMS_H_rrr1_UU
|
|
17U, // MSUBMS_U_rcrv110
|
|
0U, // MSUBMS_U_rrr2v110
|
|
17U, // MSUBMS_rcrv110
|
|
0U, // MSUBMS_rrr2v110
|
|
52U, // MSUBM_H_rrr1_LL
|
|
53U, // MSUBM_H_rrr1_LU
|
|
54U, // MSUBM_H_rrr1_UL
|
|
55U, // MSUBM_H_rrr1_UU
|
|
0U, // MSUBM_H_rrr1_v110
|
|
0U, // MSUBM_Q_rrr1_v110
|
|
17U, // MSUBM_U_rcrv110
|
|
0U, // MSUBM_U_rrr2v110
|
|
17U, // MSUBM_rcrv110
|
|
0U, // MSUBM_rrr2v110
|
|
52U, // MSUBRS_H_rrr1_LL
|
|
53U, // MSUBRS_H_rrr1_LU
|
|
54U, // MSUBRS_H_rrr1_UL
|
|
54U, // MSUBRS_H_rrr1_UL_2
|
|
55U, // MSUBRS_H_rrr1_UU
|
|
49U, // MSUBRS_H_rrr1_v110
|
|
0U, // MSUBRS_Q_rrr1_L_L
|
|
0U, // MSUBRS_Q_rrr1_U_U
|
|
49U, // MSUBRS_Q_rrr1_v110
|
|
52U, // MSUBR_H_rrr1_LL
|
|
53U, // MSUBR_H_rrr1_LU
|
|
54U, // MSUBR_H_rrr1_UL
|
|
54U, // MSUBR_H_rrr1_UL_2
|
|
55U, // MSUBR_H_rrr1_UU
|
|
49U, // MSUBR_H_rrr1_v110
|
|
0U, // MSUBR_Q_rrr1_L_L
|
|
0U, // MSUBR_Q_rrr1_U_U
|
|
49U, // MSUBR_Q_rrr1_v110
|
|
52U, // MSUBS_H_rrr1_LL
|
|
53U, // MSUBS_H_rrr1_LU
|
|
54U, // MSUBS_H_rrr1_UL
|
|
55U, // MSUBS_H_rrr1_UU
|
|
49U, // MSUBS_H_rrr1_v110
|
|
49U, // MSUBS_Q_rrr1
|
|
56U, // MSUBS_Q_rrr1_L
|
|
0U, // MSUBS_Q_rrr1_L_L
|
|
57U, // MSUBS_Q_rrr1_U
|
|
49U, // MSUBS_Q_rrr1_UU2_v110
|
|
0U, // MSUBS_Q_rrr1_U_U
|
|
49U, // MSUBS_Q_rrr1_e
|
|
56U, // MSUBS_Q_rrr1_e_L
|
|
0U, // MSUBS_Q_rrr1_e_L_L
|
|
57U, // MSUBS_Q_rrr1_e_U
|
|
0U, // MSUBS_Q_rrr1_e_U_U
|
|
17U, // MSUBS_U_rcr
|
|
17U, // MSUBS_U_rcr_e
|
|
0U, // MSUBS_U_rrr2
|
|
0U, // MSUBS_U_rrr2_e
|
|
17U, // MSUBS_rcr
|
|
17U, // MSUBS_rcr_e
|
|
0U, // MSUBS_rrr2
|
|
0U, // MSUBS_rrr2_e
|
|
0U, // MSUB_F_rrr
|
|
52U, // MSUB_H_rrr1_LL
|
|
53U, // MSUB_H_rrr1_LU
|
|
54U, // MSUB_H_rrr1_UL
|
|
55U, // MSUB_H_rrr1_UU
|
|
49U, // MSUB_H_rrr1_v110
|
|
49U, // MSUB_Q_rrr1
|
|
56U, // MSUB_Q_rrr1_L
|
|
0U, // MSUB_Q_rrr1_L_L
|
|
57U, // MSUB_Q_rrr1_U
|
|
49U, // MSUB_Q_rrr1_UU2_v110
|
|
0U, // MSUB_Q_rrr1_U_U
|
|
49U, // MSUB_Q_rrr1_e
|
|
56U, // MSUB_Q_rrr1_e_L
|
|
0U, // MSUB_Q_rrr1_e_L_L
|
|
57U, // MSUB_Q_rrr1_e_U
|
|
0U, // MSUB_Q_rrr1_e_U_U
|
|
65U, // MSUB_U_rcr
|
|
0U, // MSUB_U_rrr2
|
|
17U, // MSUB_rcr
|
|
17U, // MSUB_rcr_e
|
|
0U, // MSUB_rrr2
|
|
0U, // MSUB_rrr2_e
|
|
0U, // MTCR_rlc
|
|
4U, // MULMS_H_rr1_LL2e
|
|
5U, // MULMS_H_rr1_LU2e
|
|
6U, // MULMS_H_rr1_UL2e
|
|
7U, // MULMS_H_rr1_UU2e
|
|
4U, // MULM_H_rr1_LL2e
|
|
5U, // MULM_H_rr1_LU2e
|
|
6U, // MULM_H_rr1_UL2e
|
|
7U, // MULM_H_rr1_UU2e
|
|
0U, // MULM_U_rc
|
|
0U, // MULM_U_rr
|
|
0U, // MULM_rc
|
|
0U, // MULM_rr
|
|
4U, // MULR_H_rr1_LL2e
|
|
5U, // MULR_H_rr1_LU2e
|
|
6U, // MULR_H_rr1_UL2e
|
|
7U, // MULR_H_rr1_UU2e
|
|
1U, // MULR_H_rr_v110
|
|
0U, // MULR_Q_rr1_2LL
|
|
0U, // MULR_Q_rr1_2UU
|
|
1U, // MULR_Q_rr_v110
|
|
0U, // MULS_U_rc
|
|
0U, // MULS_U_rr2
|
|
0U, // MULS_U_rr_v110
|
|
0U, // MULS_rc
|
|
0U, // MULS_rr2
|
|
0U, // MULS_rr_v110
|
|
0U, // MUL_F_rrr
|
|
4U, // MUL_H_rr1_LL2e
|
|
5U, // MUL_H_rr1_LU2e
|
|
6U, // MUL_H_rr1_UL2e
|
|
7U, // MUL_H_rr1_UU2e
|
|
1U, // MUL_H_rr_v110
|
|
1U, // MUL_Q_rr1_2
|
|
0U, // MUL_Q_rr1_2LL
|
|
0U, // MUL_Q_rr1_2UU
|
|
8U, // MUL_Q_rr1_2_L
|
|
8U, // MUL_Q_rr1_2_Le
|
|
9U, // MUL_Q_rr1_2_U
|
|
9U, // MUL_Q_rr1_2_Ue
|
|
1U, // MUL_Q_rr1_2__e
|
|
1U, // MUL_Q_rr_v110
|
|
0U, // MUL_U_rc
|
|
0U, // MUL_U_rr2
|
|
0U, // MUL_rc
|
|
0U, // MUL_rc_e
|
|
0U, // MUL_rr2
|
|
0U, // MUL_rr2_e
|
|
0U, // MUL_rr_v110
|
|
0U, // MUL_srr
|
|
0U, // NAND_T
|
|
0U, // NAND_rc
|
|
0U, // NAND_rr
|
|
0U, // NEZ_A
|
|
0U, // NE_A
|
|
0U, // NE_rc
|
|
0U, // NE_rr
|
|
0U, // NOP_sr
|
|
0U, // NOP_sys
|
|
0U, // NOR_T
|
|
0U, // NOR_rc
|
|
0U, // NOR_rr
|
|
0U, // NOR_sr
|
|
0U, // NOR_sr_v110
|
|
0U, // NOT_sr_v162
|
|
0U, // ORN_T
|
|
0U, // ORN_rc
|
|
0U, // ORN_rr
|
|
0U, // OR_ANDN_T
|
|
0U, // OR_AND_T
|
|
0U, // OR_EQ_rc
|
|
0U, // OR_EQ_rr
|
|
0U, // OR_GE_U_rc
|
|
0U, // OR_GE_U_rr
|
|
0U, // OR_GE_rc
|
|
0U, // OR_GE_rr
|
|
0U, // OR_LT_U_rc
|
|
0U, // OR_LT_U_rr
|
|
0U, // OR_LT_rc
|
|
0U, // OR_LT_rr
|
|
0U, // OR_NE_rc
|
|
0U, // OR_NE_rr
|
|
0U, // OR_NOR_T
|
|
0U, // OR_OR_T
|
|
0U, // OR_T
|
|
0U, // OR_rc
|
|
0U, // OR_rr
|
|
0U, // OR_sc
|
|
0U, // OR_sc_v110
|
|
0U, // OR_srr
|
|
0U, // OR_srr_v110
|
|
0U, // PACK_rrr
|
|
0U, // PARITY_rr
|
|
0U, // PARITY_rr_v110
|
|
0U, // POPCNT_W_rr
|
|
0U, // Q31TOF_rr
|
|
0U, // QSEED_F_rr
|
|
0U, // RESTORE_sys
|
|
0U, // RET_sr
|
|
0U, // RET_sys
|
|
0U, // RET_sys_v110
|
|
0U, // RFE_sr
|
|
0U, // RFE_sys_sys
|
|
0U, // RFE_sys_sys_v110
|
|
0U, // RFM_sys
|
|
0U, // RSLCX_sys
|
|
0U, // RSTV_sys
|
|
0U, // RSUBS_U_rc
|
|
0U, // RSUBS_rc
|
|
0U, // RSUB_rc
|
|
0U, // RSUB_sr_sr
|
|
0U, // RSUB_sr_sr_v110
|
|
0U, // SAT_BU_rr
|
|
0U, // SAT_BU_sr
|
|
0U, // SAT_BU_sr_v110
|
|
0U, // SAT_B_rr
|
|
0U, // SAT_B_sr
|
|
0U, // SAT_B_sr_v110
|
|
0U, // SAT_HU_rr
|
|
0U, // SAT_HU_sr
|
|
0U, // SAT_HU_sr_v110
|
|
0U, // SAT_H_rr
|
|
0U, // SAT_H_sr
|
|
0U, // SAT_H_sr_v110
|
|
17U, // SELN_A_rcr_v110
|
|
0U, // SELN_A_rrr_v110
|
|
17U, // SELN_rcr
|
|
0U, // SELN_rrr
|
|
17U, // SEL_A_rcr_v110
|
|
0U, // SEL_A_rrr_v110
|
|
17U, // SEL_rcr
|
|
0U, // SEL_rrr
|
|
0U, // SHAS_rc
|
|
0U, // SHAS_rr
|
|
0U, // SHA_B_rc
|
|
0U, // SHA_B_rr
|
|
0U, // SHA_H_rc
|
|
0U, // SHA_H_rr
|
|
0U, // SHA_rc
|
|
0U, // SHA_rr
|
|
0U, // SHA_src
|
|
0U, // SHA_src_v110
|
|
0U, // SHUFFLE_rc
|
|
0U, // SH_ANDN_T
|
|
0U, // SH_AND_T
|
|
0U, // SH_B_rc
|
|
0U, // SH_B_rr
|
|
0U, // SH_EQ_rc
|
|
0U, // SH_EQ_rr
|
|
0U, // SH_GE_U_rc
|
|
0U, // SH_GE_U_rr
|
|
0U, // SH_GE_rc
|
|
0U, // SH_GE_rr
|
|
0U, // SH_H_rc
|
|
0U, // SH_H_rr
|
|
0U, // SH_LT_U_rc
|
|
0U, // SH_LT_U_rr
|
|
0U, // SH_LT_rc
|
|
0U, // SH_LT_rr
|
|
0U, // SH_NAND_T
|
|
0U, // SH_NE_rc
|
|
0U, // SH_NE_rr
|
|
0U, // SH_NOR_T
|
|
0U, // SH_ORN_T
|
|
0U, // SH_OR_T
|
|
0U, // SH_XNOR_T
|
|
0U, // SH_XOR_T
|
|
0U, // SH_rc
|
|
0U, // SH_rr
|
|
0U, // SH_src
|
|
0U, // SH_src_v110
|
|
0U, // STLCX_abs
|
|
0U, // STLCX_bo_bso
|
|
0U, // STUCX_abs
|
|
0U, // STUCX_bo_bso
|
|
0U, // ST_A_abs
|
|
0U, // ST_A_bo_bso
|
|
0U, // ST_A_bo_c
|
|
0U, // ST_A_bo_pos
|
|
0U, // ST_A_bo_pre
|
|
0U, // ST_A_bo_r
|
|
0U, // ST_A_bol
|
|
0U, // ST_A_sc
|
|
0U, // ST_A_sro
|
|
0U, // ST_A_sro_v110
|
|
0U, // ST_A_ssr
|
|
0U, // ST_A_ssr_pos
|
|
0U, // ST_A_ssr_pos_v110
|
|
0U, // ST_A_ssr_v110
|
|
0U, // ST_A_ssro
|
|
0U, // ST_A_ssro_v110
|
|
0U, // ST_B_abs
|
|
0U, // ST_B_bo_bso
|
|
0U, // ST_B_bo_c
|
|
0U, // ST_B_bo_pos
|
|
0U, // ST_B_bo_pre
|
|
0U, // ST_B_bo_r
|
|
0U, // ST_B_bol
|
|
0U, // ST_B_sro
|
|
0U, // ST_B_sro_v110
|
|
0U, // ST_B_ssr
|
|
0U, // ST_B_ssr_pos
|
|
0U, // ST_B_ssr_pos_v110
|
|
0U, // ST_B_ssr_v110
|
|
0U, // ST_B_ssro
|
|
0U, // ST_B_ssro_v110
|
|
0U, // ST_DA_abs
|
|
0U, // ST_DA_bo_bso
|
|
0U, // ST_DA_bo_c
|
|
0U, // ST_DA_bo_pos
|
|
0U, // ST_DA_bo_pre
|
|
0U, // ST_DA_bo_r
|
|
0U, // ST_D_abs
|
|
0U, // ST_D_bo_bso
|
|
0U, // ST_D_bo_c
|
|
0U, // ST_D_bo_pos
|
|
0U, // ST_D_bo_pre
|
|
0U, // ST_D_bo_r
|
|
0U, // ST_H_abs
|
|
0U, // ST_H_bo_bso
|
|
0U, // ST_H_bo_c
|
|
0U, // ST_H_bo_pos
|
|
0U, // ST_H_bo_pre
|
|
0U, // ST_H_bo_r
|
|
0U, // ST_H_bol
|
|
0U, // ST_H_sro
|
|
0U, // ST_H_sro_v110
|
|
0U, // ST_H_ssr
|
|
0U, // ST_H_ssr_pos
|
|
0U, // ST_H_ssr_pos_v110
|
|
0U, // ST_H_ssr_v110
|
|
0U, // ST_H_ssro
|
|
0U, // ST_H_ssro_v110
|
|
0U, // ST_Q_abs
|
|
0U, // ST_Q_bo_bso
|
|
0U, // ST_Q_bo_c
|
|
0U, // ST_Q_bo_pos
|
|
0U, // ST_Q_bo_pre
|
|
0U, // ST_Q_bo_r
|
|
0U, // ST_T
|
|
0U, // ST_W_abs
|
|
0U, // ST_W_bo_bso
|
|
0U, // ST_W_bo_c
|
|
0U, // ST_W_bo_pos
|
|
0U, // ST_W_bo_pre
|
|
0U, // ST_W_bo_r
|
|
0U, // ST_W_bol
|
|
0U, // ST_W_sc
|
|
0U, // ST_W_sro
|
|
0U, // ST_W_sro_v110
|
|
0U, // ST_W_ssr
|
|
0U, // ST_W_ssr_pos
|
|
0U, // ST_W_ssr_pos_v110
|
|
0U, // ST_W_ssr_v110
|
|
0U, // ST_W_ssro
|
|
0U, // ST_W_ssro_v110
|
|
0U, // SUBC_rr
|
|
1U, // SUBSC_A_rr
|
|
0U, // SUBS_BU_rr
|
|
0U, // SUBS_B_rr
|
|
0U, // SUBS_HU_rr
|
|
0U, // SUBS_H_rr
|
|
0U, // SUBS_U_rr
|
|
0U, // SUBS_rr
|
|
0U, // SUBS_srr
|
|
0U, // SUBX_rr
|
|
0U, // SUB_A_rr
|
|
0U, // SUB_A_sc
|
|
0U, // SUB_A_sc_v110
|
|
0U, // SUB_B_rr
|
|
0U, // SUB_F_rrr
|
|
0U, // SUB_H_rr
|
|
0U, // SUB_rr
|
|
0U, // SUB_srr
|
|
0U, // SUB_srr_15a
|
|
0U, // SUB_srr_a15
|
|
0U, // SVLCX_sys
|
|
0U, // SWAPMSK_W_bo_bso
|
|
0U, // SWAPMSK_W_bo_c
|
|
0U, // SWAPMSK_W_bo_pos
|
|
0U, // SWAPMSK_W_bo_pre
|
|
0U, // SWAPMSK_W_bo_r
|
|
0U, // SWAP_A_abs
|
|
0U, // SWAP_A_bo_bso
|
|
0U, // SWAP_A_bo_c
|
|
0U, // SWAP_A_bo_pos
|
|
0U, // SWAP_A_bo_pre
|
|
0U, // SWAP_A_bo_r
|
|
0U, // SWAP_W_abs
|
|
0U, // SWAP_W_bo_bso
|
|
0U, // SWAP_W_bo_c
|
|
0U, // SWAP_W_bo_indexed
|
|
0U, // SWAP_W_bo_pos
|
|
0U, // SWAP_W_bo_pre
|
|
0U, // SWAP_W_bo_r
|
|
0U, // SYSCALL_rc
|
|
0U, // TLBDEMAP_rr
|
|
0U, // TLBFLUSH_A_rr
|
|
0U, // TLBFLUSH_B_rr
|
|
0U, // TLBMAP_rr
|
|
0U, // TLBPROBE_A_rr
|
|
0U, // TLBPROBE_I_rr
|
|
0U, // TRAPSV_sys
|
|
0U, // TRAPV_sys
|
|
0U, // UNPACK_rr_rr
|
|
0U, // UNPACK_rr_rr_v110
|
|
0U, // UPDFL_rr
|
|
0U, // UTOF_rr
|
|
0U, // WAIT_sys
|
|
0U, // XNOR_T
|
|
0U, // XNOR_rc
|
|
0U, // XNOR_rr
|
|
0U, // XOR_EQ_rc
|
|
0U, // XOR_EQ_rr
|
|
0U, // XOR_GE_U_rc
|
|
0U, // XOR_GE_U_rr
|
|
0U, // XOR_GE_rc
|
|
0U, // XOR_GE_rr
|
|
0U, // XOR_LT_U_rc
|
|
0U, // XOR_LT_U_rr
|
|
0U, // XOR_LT_rc
|
|
0U, // XOR_LT_rr
|
|
0U, // XOR_NE_rc
|
|
0U, // XOR_NE_rr
|
|
0U, // XOR_T
|
|
0U, // XOR_rc
|
|
0U, // XOR_rr
|
|
0U, // XOR_srr
|
|
};
|
|
|
|
// Emit the opcode for the instruction.
|
|
uint64_t Bits = 0;
|
|
Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0;
|
|
Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32;
|
|
MnemonicBitsInfo MBI = {AsmStrs+(Bits & 4095)-1, Bits};
|
|
return MBI;
|
|
|
|
}
|
|
/// printInstruction - This method is automatically generated by tablegen
|
|
/// from the instruction set description.
|
|
void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
|
|
SStream_concat0(O, "");
|
|
MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);
|
|
|
|
SStream_concat0(O, MnemonicInfo.first);
|
|
|
|
uint64_t Bits = MnemonicInfo.second;
|
|
assert(Bits != 0 && "Cannot print this instruction.");
|
|
|
|
// Fragment 0 encoded into 4 bits for 13 unique commands.
|
|
switch ((Bits >> 12) & 15) {
|
|
default: assert(0 && "Invalid command number.");
|
|
case 0:
|
|
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
|
|
printOperand(MI, 0, O);
|
|
break;
|
|
case 2:
|
|
// AND_sc, AND_sc_v110, BISR_sc, BISR_sc_v110, LD_A_sc, LD_W_sc, MOV_sc, ...
|
|
printZExtImm_8(MI, 0, O);
|
|
break;
|
|
case 3:
|
|
// BISR_rc, BISR_rc_v161, SYSCALL_rc
|
|
printSExtImm_9(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// CALLA_b, CALL_b, FCALLA_b, FCALL_b, JA_b, JLA_b, JL_b, J_b
|
|
printDisp24Imm(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// CALL_sb, JNZ_sb, JNZ_sb_v110, JZ_sb, JZ_sb_v110, J_sb, J_sb_v110
|
|
printDisp8Imm(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// CMPSWAP_W_bo_bso, CMPSWAP_W_bo_c, CMPSWAP_W_bo_pos, CMPSWAP_W_bo_pre, ...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 7:
|
|
// JEQ_sbc1, JEQ_sbc2, JEQ_sbc_v110, JNE_sbc1, JNE_sbc2, JNE_sbc_v110
|
|
printSExtImm_4(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printDisp4Imm(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// LDLCX_abs, LDUCX_abs, STLCX_abs, STUCX_abs, ST_T
|
|
printOff18Imm(MI, 0, O);
|
|
break;
|
|
case 9:
|
|
// LDMST_abs, ST_A_abs, ST_B_abs, ST_DA_abs, ST_D_abs, ST_H_abs, ST_Q_abs...
|
|
printOff18Imm(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// LOOPU_brr
|
|
printDisp15Imm(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// MTCR_rlc
|
|
printSExtImm_16(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// ST_A_ssro, ST_A_ssro_v110, ST_B_ssro, ST_B_ssro_v110, ST_H_ssro, ST_H_...
|
|
printZExtImm_4(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 4 bits for 16 unique commands.
|
|
switch ((Bits >> 16) & 15) {
|
|
default: assert(0 && "Invalid command number.");
|
|
case 0:
|
|
// ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 1:
|
|
// ADD_src_a15, ADD_srr_a15, CADDN_src, CADDN_srr_v110, CADD_src, CADD_sr...
|
|
SStream_concat0(O, ", %d15, ");
|
|
break;
|
|
case 2:
|
|
// AND_sc, AND_sc_v110, BISR_sc, BISR_sc_v110, CALLI_rr, CALLI_rr_v110, D...
|
|
return;
|
|
break;
|
|
case 3:
|
|
// CACHEA_I_bo_bso, CACHEA_I_bo_pre, CACHEA_WI_bo_bso, CACHEA_WI_bo_pre, ...
|
|
SStream_concat1(O, ']');
|
|
break;
|
|
case 4:
|
|
// CACHEA_I_bo_c, CACHEA_WI_bo_c, CACHEA_W_bo_c, CMPSWAP_W_bo_c, LDMST_bo...
|
|
SStream_concat0(O, "+c]");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 5:
|
|
// CACHEA_I_bo_pos, CACHEA_WI_bo_pos, CACHEA_W_bo_pos, CACHEI_I_bo_pos, C...
|
|
SStream_concat0(O, "+]");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 6:
|
|
// CACHEA_I_bo_r, CACHEA_WI_bo_r, CACHEA_W_bo_r
|
|
SStream_concat0(O, "+r]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// CMPSWAP_W_bo_r, LDMST_bo_r, SWAP_A_bo_r, SWAP_W_bo_r
|
|
SStream_concat0(O, "+r], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 8:
|
|
// LD_A_bo_bso, LD_A_bo_c, LD_A_bo_pos, LD_A_bo_r, LD_A_bol, LD_A_slr, LD...
|
|
SStream_concat0(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 9:
|
|
// LD_A_bo_pre, LD_BU_bo_pre, LD_B_bo_pre, LD_DA_bo_pre, LD_D_bo_pre, LD_...
|
|
SStream_concat0(O, ", [+");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 10:
|
|
// LD_A_slro, LD_A_slro_v110, LD_BU_slro, LD_BU_slro_v110, LD_B_slro_v110...
|
|
SStream_concat0(O, ", [%a15]");
|
|
set_mem_access(MI, true);
|
|
printZExtImm_4(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// ST_A_sc
|
|
SStream_concat0(O, ", %a15");
|
|
return;
|
|
break;
|
|
case 12:
|
|
// ST_A_ssr, ST_A_ssr_v110, ST_B_ssr, ST_B_ssr_v110, ST_H_ssr, ST_H_ssr_v...
|
|
SStream_concat0(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// ST_A_ssr_pos, ST_A_ssr_pos_v110, ST_B_ssr_pos, ST_B_ssr_pos_v110, ST_H...
|
|
SStream_concat0(O, "+], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// ST_W_sc
|
|
SStream_concat0(O, ", %d15");
|
|
return;
|
|
break;
|
|
case 15:
|
|
// SWAP_W_bo_indexed
|
|
SStream_concat0(O, "+i], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 4 bits for 14 unique commands.
|
|
switch ((Bits >> 20) & 15) {
|
|
default: assert(0 && "Invalid command number.");
|
|
case 0:
|
|
// ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 1:
|
|
// ABSS_B_rr_v110, ABSS_rr, ADDSC_AT_rr, ADDSC_A_rr, CADDN_A_rcr_v110, CA...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 2:
|
|
// ADD_A_src, ADD_src, ADD_src_15a, ADD_src_a15, CADDN_src, CADD_src, CMO...
|
|
printSExtImm_4(MI, 1, O);
|
|
break;
|
|
case 3:
|
|
// ADD_F_rrr, CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRC...
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 4:
|
|
// CACHEA_I_bo_bso, CACHEA_I_bo_c, CACHEA_I_bo_pos, CACHEA_I_bo_pre, CACH...
|
|
printSExtImm_10(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// CMPSWAP_W_bo_bso, CMPSWAP_W_bo_c, CMPSWAP_W_bo_pos, CMPSWAP_W_bo_pre, ...
|
|
printSExtImm_10(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 6:
|
|
// CMPSWAP_W_bo_r, LDMST_bo_r, ST_A_bo_pos, ST_A_bo_pre, ST_B_bo_pos, ST_...
|
|
printOperand(MI, 0, O);
|
|
break;
|
|
case 7:
|
|
// JEQ_sbr1, JEQ_sbr2, JEQ_sbr_v110, JGEZ_sbr, JGEZ_sbr_v110, JGTZ_sbr, J...
|
|
printDisp4Imm(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// JGE_U_brc, JLT_U_brc, JLT_brc, JNED_brc, JNEI_brc, LD_A_sro, LD_A_sro_...
|
|
printZExtImm_4(MI, 1, O);
|
|
break;
|
|
case 9:
|
|
// JNZ_A_brr, JZ_A_brr, LOOP_brr
|
|
printDisp15Imm(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// LD_A_abs, LD_BU_abs, LD_B_abs, LD_DA_abs, LD_D_abs, LD_HU_abs, LD_H_ab...
|
|
printOff18Imm(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// MFCR_rlc, MOVH_A_rlc, MOVH_rlc, MOV_U_rlc, MOV_rlc_e
|
|
printZExtImm_16(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// MOV_rlc
|
|
printSExtImm_16(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// ST_A_bol, ST_B_bol, ST_H_bol, ST_W_bol
|
|
printSExtImm_16(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 3 encoded into 4 bits for 14 unique commands.
|
|
switch ((Bits >> 24) & 15) {
|
|
default: assert(0 && "Invalid command number.");
|
|
case 0:
|
|
// ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 1:
|
|
// ABSS_B_rr_v110, ABSS_rr, ABS_B_rr, ABS_H_rr, ABS_rr, ADDS_srr, ADD_A_s...
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADDSC_A_srrs
|
|
SStream_concat0(O, ", %d15, ");
|
|
printZExtImm_2(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ADD_F_rrr, CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRC...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 4:
|
|
// CMPSWAP_W_bo_bso, CMPSWAP_W_bo_c, CMPSWAP_W_bo_pos, CMPSWAP_W_bo_pre, ...
|
|
printOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// DVADJ_rrr, DVADJ_rrr_v110, DVSTEP_U_rrr, DVSTEP_U_rrrv110, DVSTEP_rrr,...
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// LD_A_bo_bso, LD_A_bo_pre, LD_A_bol, LD_A_slr, LD_A_slr_v110, LD_BU_bo_...
|
|
SStream_concat1(O, ']');
|
|
break;
|
|
case 7:
|
|
// LD_A_bo_c, LD_BU_bo_c, LD_B_bo_c, LD_DA_bo_c, LD_D_bo_c, LD_HU_bo_c, L...
|
|
SStream_concat0(O, "+c]");
|
|
set_mem_access(MI, false);
|
|
printSExtImm_10(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// LD_A_bo_pos, LD_A_slr_post, LD_A_slr_post_v110, LD_BU_bo_pos, LD_BU_sl...
|
|
SStream_concat0(O, "+]");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 9:
|
|
// LD_A_bo_r, LD_BU_bo_r, LD_B_bo_r, LD_DA_bo_r, LD_D_bo_r, LD_HU_bo_r, L...
|
|
SStream_concat0(O, "+r]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// MULR_Q_rr1_2LL, MUL_Q_rr1_2LL
|
|
SStream_concat0(O, "l, ");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "l, ");
|
|
printZExtImm_2(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// MULR_Q_rr1_2UU, MUL_Q_rr1_2UU
|
|
SStream_concat0(O, "u, ");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "u, ");
|
|
printZExtImm_2(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// ST_A_sro, ST_A_sro_v110
|
|
SStream_concat0(O, ", %a15");
|
|
return;
|
|
break;
|
|
case 13:
|
|
// ST_B_sro, ST_B_sro_v110, ST_H_sro, ST_H_sro_v110, ST_W_sro, ST_W_sro_v...
|
|
SStream_concat0(O, ", %d15");
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 4 encoded into 4 bits for 15 unique commands.
|
|
switch ((Bits >> 28) & 15) {
|
|
default: assert(0 && "Invalid command number.");
|
|
case 0:
|
|
// ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 1:
|
|
// ABSDIF_rc, ADDC_rc, ADDS_U_rc, ADDS_rc, ADDX_rc, ADD_rc, ANDN_rc, AND_...
|
|
printSExtImm_9(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADDIH_A_rlc, ADDIH_rlc
|
|
printZExtImm_16(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ADDI_rlc, LD_A_bol, LD_BU_bol, LD_B_bol, LD_HU_bol, LD_H_bol, LD_W_bol...
|
|
printSExtImm_16(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ADDSC_AT_rr, ADDSC_A_rr, CADDN_A_rcr_v110, CADDN_rcr, CADD_A_rcr_v110,...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 5:
|
|
// ADDSC_A_srrs_v110
|
|
printZExtImm_2(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ADD_F_rrr, LD_A_slr, LD_A_slr_post, LD_A_slr_post_v110, LD_A_slr_v110,...
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ANDN_T, AND_ANDN_T, AND_AND_T, AND_NOR_T, AND_OR_T, AND_T, INSN_T, INS...
|
|
printZExtImm_4(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printZExtImm_4(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// CADDN_A_rrr_v110, CADDN_rrr, CADD_A_rrr_v110, CADD_rrr, CRCN_rrr, CSUB...
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 9:
|
|
// EXTR_U_rrrw, EXTR_rrrw, IMASK_rrrw, INSERT_rcrw
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 10:
|
|
// JEQ_A_brr, JEQ_brc, JEQ_brr, JGE_U_brc, JGE_U_brr, JGE_brc, JGE_brr, J...
|
|
printDisp15Imm(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// LD_A_bo_bso, LD_A_bo_pos, LD_A_bo_pre, LD_BU_bo_bso, LD_BU_bo_pos, LD_...
|
|
printSExtImm_10(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// MADDRS_Q_rrr1_L_L, MADDR_Q_rrr1_L_L, MADDS_Q_rrr1_L_L, MADDS_Q_rrr1_e_...
|
|
SStream_concat0(O, "l, ");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "l, ");
|
|
printZExtImm_2(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// MADDRS_Q_rrr1_U_U, MADDR_Q_rrr1_U_U, MADDS_Q_rrr1_U_U, MADDS_Q_rrr1_e_...
|
|
SStream_concat0(O, "u, ");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, "u, ");
|
|
printZExtImm_2(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// OR_rc
|
|
printZExtImm_9(MI, 2, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 5 encoded into 4 bits for 10 unique commands.
|
|
switch ((Bits >> 32) & 15) {
|
|
default: assert(0 && "Invalid command number.");
|
|
case 0:
|
|
// ABSDIFS_B_rr_v110, ABSDIFS_H_rr, ABSDIFS_rc, ABSDIFS_rr, ABSDIF_B_rr, ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADDSC_A_rr, ADDSC_A_rr_v110, CADDN_A_rcr_v110, CADDN_rcr, CADD_A_rcr_v...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 2:
|
|
// EXTR_U_rrrw, EXTR_rrrw, IMASK_rrrw
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// INSERT_rcrw
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// MADDMS_H_rrr1_LL, MADDM_H_rrr1_LL, MADDRS_H_rrr1_LL, MADDR_H_rrr1_LL, ...
|
|
SStream_concat0(O, "ll, ");
|
|
break;
|
|
case 5:
|
|
// MADDMS_H_rrr1_LU, MADDM_H_rrr1_LU, MADDRS_H_rrr1_LU, MADDR_H_rrr1_LU, ...
|
|
SStream_concat0(O, "lu, ");
|
|
break;
|
|
case 6:
|
|
// MADDMS_H_rrr1_UL, MADDM_H_rrr1_UL, MADDRS_H_rrr1_UL, MADDRS_H_rrr1_UL_...
|
|
SStream_concat0(O, "ul, ");
|
|
break;
|
|
case 7:
|
|
// MADDMS_H_rrr1_UU, MADDM_H_rrr1_UU, MADDRS_H_rrr1_UU, MADDR_H_rrr1_UU, ...
|
|
SStream_concat0(O, "uu, ");
|
|
break;
|
|
case 8:
|
|
// MADDS_Q_rrr1_L, MADDS_Q_rrr1_e_L, MADD_Q_rrr1_L, MADD_Q_rrr1_e_L, MSUB...
|
|
SStream_concat0(O, "l, ");
|
|
break;
|
|
case 9:
|
|
// MADDS_Q_rrr1_U, MADDS_Q_rrr1_e_U, MADD_Q_rrr1_U, MADD_Q_rrr1_e_U, MSUB...
|
|
SStream_concat0(O, "u, ");
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 6 encoded into 3 bits for 5 unique commands.
|
|
switch ((Bits >> 36) & 7) {
|
|
default: assert(0 && "Invalid command number.");
|
|
case 0:
|
|
// ADDSC_A_rr, ADDSC_A_rr_v110, DIFSC_A_rr_v110, MULMS_H_rr1_LL2e, MULMS_...
|
|
printZExtImm_2(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 1:
|
|
// CADDN_A_rcr_v110, CADDN_rcr, CADD_A_rcr_v110, CADD_rcr, MADDMS_rcr_v11...
|
|
printSExtImm_9(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// DEXTR_rrpw, DEXTR_rrrr, EXTR_U_rrpw, EXTR_rrpw, IMASK_rcpw, IMASK_rcrw...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 3:
|
|
// MADDMS_H_rrr1_LL, MADDMS_H_rrr1_LU, MADDMS_H_rrr1_UL, MADDMS_H_rrr1_UU...
|
|
printZExtImm_2(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// MADDMS_U_rcr_v110, MADDM_U_rcr_v110, MADD_U_rcr, MSUB_U_rcr
|
|
printZExtImm_9(MI, 3, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 7 encoded into 1 bits for 2 unique commands.
|
|
if ((Bits >> 39) & 1) {
|
|
// INSERT_rcpw, INSERT_rrpw, INSERT_rrrr, INSERT_rrrw
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
} else {
|
|
// DEXTR_rrpw, DEXTR_rrrr, EXTR_U_rrpw, EXTR_rrpw, IMASK_rcpw, IMASK_rcrw...
|
|
return;
|
|
}
|
|
|
|
}
|
|
|
|
|
|
/// getRegisterName - This method is automatically generated by tblgen
|
|
/// from the register set description. This returns the assembler name
|
|
/// for the specified register.
|
|
const char *getRegisterName(unsigned RegNo) {
|
|
assert(RegNo && RegNo < 61 && "Invalid register number!");
|
|
|
|
static const char AsmStrs[] = {
|
|
/* 0 */ "d10\0"
|
|
/* 4 */ "e10\0"
|
|
/* 8 */ "p10\0"
|
|
/* 12 */ "a0\0"
|
|
/* 15 */ "d0\0"
|
|
/* 18 */ "e0\0"
|
|
/* 21 */ "p0\0"
|
|
/* 24 */ "A10_A11\0"
|
|
/* 32 */ "a11\0"
|
|
/* 36 */ "d11\0"
|
|
/* 40 */ "A0_A1\0"
|
|
/* 46 */ "a1\0"
|
|
/* 49 */ "d1\0"
|
|
/* 52 */ "a12\0"
|
|
/* 56 */ "d12\0"
|
|
/* 60 */ "e12\0"
|
|
/* 64 */ "p12\0"
|
|
/* 68 */ "a2\0"
|
|
/* 71 */ "d2\0"
|
|
/* 74 */ "e2\0"
|
|
/* 77 */ "p2\0"
|
|
/* 80 */ "A12_A13\0"
|
|
/* 88 */ "a13\0"
|
|
/* 92 */ "d13\0"
|
|
/* 96 */ "A2_A3\0"
|
|
/* 102 */ "a3\0"
|
|
/* 105 */ "d3\0"
|
|
/* 108 */ "a14\0"
|
|
/* 112 */ "d14\0"
|
|
/* 116 */ "e14\0"
|
|
/* 120 */ "p14\0"
|
|
/* 124 */ "a4\0"
|
|
/* 127 */ "d4\0"
|
|
/* 130 */ "e4\0"
|
|
/* 133 */ "p4\0"
|
|
/* 136 */ "A14_A15\0"
|
|
/* 144 */ "a15\0"
|
|
/* 148 */ "d15\0"
|
|
/* 152 */ "A4_A5\0"
|
|
/* 158 */ "a5\0"
|
|
/* 161 */ "d5\0"
|
|
/* 164 */ "a6\0"
|
|
/* 167 */ "d6\0"
|
|
/* 170 */ "e6\0"
|
|
/* 173 */ "p6\0"
|
|
/* 176 */ "A6_A7\0"
|
|
/* 182 */ "a7\0"
|
|
/* 185 */ "d7\0"
|
|
/* 188 */ "a8\0"
|
|
/* 191 */ "d8\0"
|
|
/* 194 */ "e8\0"
|
|
/* 197 */ "p8\0"
|
|
/* 200 */ "A8_A9\0"
|
|
/* 206 */ "a9\0"
|
|
/* 209 */ "d9\0"
|
|
/* 212 */ "pc\0"
|
|
/* 215 */ "pcxi\0"
|
|
/* 220 */ "sp\0"
|
|
/* 223 */ "psw\0"
|
|
/* 227 */ "fcx\0"
|
|
};
|
|
static const uint8_t RegAsmOffset[] = {
|
|
227, 212, 215, 223, 12, 46, 68, 102, 124, 158, 164, 182, 188, 206,
|
|
220, 32, 52, 88, 108, 144, 15, 49, 71, 105, 127, 161, 167, 185,
|
|
191, 209, 0, 36, 56, 92, 112, 148, 18, 74, 130, 170, 194, 4,
|
|
60, 116, 21, 77, 133, 173, 197, 8, 64, 120, 40, 96, 152, 176,
|
|
200, 24, 80, 136,
|
|
};
|
|
|
|
assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
|
|
"Invalid alt name index for register!");
|
|
return AsmStrs+RegAsmOffset[RegNo-1];
|
|
}
|
|
#ifdef PRINT_ALIAS_INSTR
|
|
#undef PRINT_ALIAS_INSTR
|
|
|
|
bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
|
|
return false;
|
|
}
|
|
|
|
#endif // PRINT_ALIAS_INSTR
|