UefiCpuPkg: fix issue when SMM profile is enabled
This commit is to fix smm code assert issue when SMM Profile is enabled. When SMM Profile is enabled, the function InitProtectedMemRange() retrives MMIO ranges from GCD and store the MMIO ranges in the mProtectionMemRange. When ReadyToLock, the function InitPaging() modifies the page table based on the mProtectionMemRange. If the MMIO ranges in mProtectionMemRange is not 4k aligned, code will assert when modifying page table. In this commit, we skip the MMIO ranges that BaseAddress and Length are not 4k aligned when creating mProtectionMemRange. This will only cause each access to the skipped MMIO range to be logged. In current failure case on QEMU and QSP SimicsOpenBoard, the skipped MMIO range is [0xFED00000, 0xFED00400] for HPET. Considering that the probability of HPET MMIO range being accessed is very small in SMM, the solution in this commit is acceptable and simple. Signed-off-by: Dun Tan <dun.tan@intel.com>
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@ -438,8 +438,23 @@ InitProtectedMemRange (
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&MemorySpaceMap
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);
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for (Index = 0; Index < NumberOfDescriptors; Index++) {
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if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) {
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NumberOfAddedDescriptors++;
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if ((MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo)) {
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if (ADDRESS_IS_ALIGNED (MemorySpaceMap[Index].BaseAddress, SIZE_4KB) &&
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(MemorySpaceMap[Index].Length % SIZE_4KB == 0))
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{
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NumberOfAddedDescriptors++;
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} else {
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//
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// Skip the MMIO range that BaseAddress and Length are not 4k aligned since
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// the minimum granularity of the page table is 4k
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//
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DEBUG ((
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DEBUG_WARN,
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"MMIO range [0x%lx, 0x%lx] is skipped since it is not 4k aligned.\n",
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MemorySpaceMap[Index].BaseAddress,
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MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length
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));
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}
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}
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}
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@ -486,15 +501,16 @@ InitProtectedMemRange (
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// Create MMIO ranges which are set to present and execution-disable.
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//
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for (Index = 0; Index < NumberOfDescriptors; Index++) {
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if (MemorySpaceMap[Index].GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo) {
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continue;
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if ((MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&
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ADDRESS_IS_ALIGNED (MemorySpaceMap[Index].BaseAddress, SIZE_4KB) &&
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(MemorySpaceMap[Index].Length % SIZE_4KB == 0))
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{
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mProtectionMemRange[NumberOfProtectRange].Range.Base = MemorySpaceMap[Index].BaseAddress;
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mProtectionMemRange[NumberOfProtectRange].Range.Top = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length;
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mProtectionMemRange[NumberOfProtectRange].Present = TRUE;
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mProtectionMemRange[NumberOfProtectRange].Nx = TRUE;
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NumberOfProtectRange++;
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}
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mProtectionMemRange[NumberOfProtectRange].Range.Base = MemorySpaceMap[Index].BaseAddress;
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mProtectionMemRange[NumberOfProtectRange].Range.Top = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length;
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mProtectionMemRange[NumberOfProtectRange].Present = TRUE;
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mProtectionMemRange[NumberOfProtectRange].Nx = TRUE;
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NumberOfProtectRange++;
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}
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//
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