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UefiCpuPkg: Update code to use new structure field names 

Due to coding style fix of the structure definition in BaseLib.h, all
code referencing those structure must be updated accordingly.

Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
This commit is contained in:
Jian J Wang 2017-12-26 08:43:59 +08:00 committed by Star Zeng
parent 5e2ee2f5f4
commit 56649f4301
3 changed files with 16 additions and 16 deletions
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24
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
View File

@ -216,7 +216,7 @@ ArchSetupExcpetionStack (
TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
TssDesc->Bits.P = 1; TssDesc->Bits.Present = 1;
TssDesc->Bits.LimitHigh = 0; TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24); TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
@ -240,7 +240,7 @@ ArchSetupExcpetionStack (
TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
TssDesc->Bits.P = 1; TssDesc->Bits.Present = 1;
TssDesc->Bits.LimitHigh = 0; TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24); TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
@ -253,17 +253,17 @@ ArchSetupExcpetionStack (
continue; continue;
} }
Tss->EIP = (UINT32)(TemplateMap.ExceptionStart Tss->Eip = (UINT32)(TemplateMap.ExceptionStart
+ Vector * TemplateMap.ExceptionStubHeaderSize); + Vector * TemplateMap.ExceptionStubHeaderSize);
Tss->EFLAGS = 0x2; Tss->Eflags = 0x2;
Tss->ESP = StackTop; Tss->Esp = StackTop;
Tss->CR3 = AsmReadCr3 (); Tss->Cr3 = AsmReadCr3 ();
Tss->ES = AsmReadEs (); Tss->Es = AsmReadEs ();
Tss->CS = AsmReadCs (); Tss->Cs = AsmReadCs ();
Tss->SS = AsmReadSs (); Tss->Ss = AsmReadSs ();
Tss->DS = AsmReadDs (); Tss->Ds = AsmReadDs ();
Tss->FS = AsmReadFs (); Tss->Fs = AsmReadFs ();
Tss->GS = AsmReadGs (); Tss->Gs = AsmReadGs ();
StackTop -= StackSwitchData->Ia32.KnownGoodStackSize; StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;

6
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
View File

@ -186,7 +186,7 @@ ArchSetupExcpetionStack (
// //
TssDesc = StackSwitchData->X64.ExceptionTssDesc; TssDesc = StackSwitchData->X64.ExceptionTssDesc;
Tss = StackSwitchData->X64.ExceptionTss; Tss = StackSwitchData->X64.ExceptionTss;
if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) { if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->Ist)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -221,7 +221,7 @@ ArchSetupExcpetionStack (
TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16); TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
TssDesc->Bits.P = 1; TssDesc->Bits.Present = 1;
TssDesc->Bits.LimitHigh = 0; TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24); TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32); TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
@ -236,7 +236,7 @@ ArchSetupExcpetionStack (
// //
// Fixup IST // Fixup IST
// //
Tss->IST[Index] = StackTop; Tss->Ist[Index] = StackTop;
StackTop -= StackSwitchData->X64.KnownGoodStackSize; StackTop -= StackSwitchData->X64.KnownGoodStackSize;
// //

2
UefiCpuPkg/Library/MpInitLib/MpLib.c
View File

@ -243,7 +243,7 @@ RestoreVolatileRegisters (
VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) { VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) {
Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base + Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base +
VolatileRegisters->Tr); VolatileRegisters->Tr);
if (Tss->Bits.P == 1) { if (Tss->Bits.Present == 1) {
Tss->Bits.Type &= 0xD; // 1101 - Clear busy bit just in case Tss->Bits.Type &= 0xD; // 1101 - Clear busy bit just in case
AsmWriteTr (VolatileRegisters->Tr); AsmWriteTr (VolatileRegisters->Tr);
} }