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Add code to identify D0 stepping ValleyView SoC. 

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>




git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17034 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Shifei Lu 2015-03-10 03:16:48 +00:00 committed by zwei4
parent c01934fb18
commit 8268a01d2c
2 changed files with 8 additions and 1 deletions
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2
Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h
View File

@ -119,6 +119,8 @@ typedef enum {
#define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27) #define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27)
#define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17) #define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17)
#define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27) #define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27)
#define V_PCH_LPC_RID_E 0x10 // D0 Stepping (17 x 17)
#define V_PCH_LPC_RID_F 0x11 // D0 Stepping (25 x 27)
#define R_PCH_LPC_MLT 0x0D // Master Latency Timer #define R_PCH_LPC_MLT 0x0D // Master Latency Timer
#define B_PCH_LPC_MLT_MLC 0xF8 // Master Latency Count #define B_PCH_LPC_MLT_MLC 0xF8 // Master Latency Count

7
Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c
View File

@ -83,7 +83,12 @@ PchStepping (
case V_PCH_LPC_RID_D: case V_PCH_LPC_RID_D:
return PchC0; return PchC0;
break; break;
case V_PCH_LPC_RID_E:
case V_PCH_LPC_RID_F:
return PchD0;
break;
default: default:
return PchSteppingMax; return PchSteppingMax;
break; break;