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ArmPkg: ArmGic: Cast CpuTarget to UINT32 for legacy GIC 

The current code path supporting `PcdArmGicV3WithV2Legacy` will read 32
bit CPU target and try to program ARM_GIC_ICDIPTR. However, all these
operations are 32bit wide.

This change casts the CpuTarget variable to be UINT32 before calling
MMIO read.

Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>

Signed-off-by: Kun Qin <kun.qin@microsoft.com>
This commit is contained in:
Kun Qin 2024-10-10 15:19:45 -07:00 committed by mergify[bot]
parent 95972f966e
commit 957fcbe7a3
1 changed files with 4 additions and 1 deletions
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5
ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
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@ -374,7 +374,6 @@ GicV3DxeInitialize (
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index; UINTN Index;
UINT64 CpuTarget;
UINT64 MpId; UINT64 MpId;
// Make sure the Interrupt Controller Protocol is not already installed in // Make sure the Interrupt Controller Protocol is not already installed in
@ -406,6 +405,8 @@ GicV3DxeInitialize (
// Targets the interrupts to the Primary Cpu // Targets the interrupts to the Primary Cpu
if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
UINT32 CpuTarget;
// Only Primary CPU will run this code. We can identify our GIC CPU ID by // Only Primary CPU will run this code. We can identify our GIC CPU ID by
// reading the GIC Distributor Target register. The 8 first // reading the GIC Distributor Target register. The 8 first
// GICD_ITARGETSRn are banked to each connected CPU. These 8 registers // GICD_ITARGETSRn are banked to each connected CPU. These 8 registers
@ -428,6 +429,8 @@ GicV3DxeInitialize (
} }
} }
} else { } else {
UINT64 CpuTarget;
MpId = ArmReadMpidr (); MpId = ArmReadMpidr ();
CpuTarget = MpId & CpuTarget = MpId &
(ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3); (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);