From c60d36b4d1ee1f69b7cca897d3621dfa951895c2 Mon Sep 17 00:00:00 2001 From: Jiewen Yao Date: Sat, 3 Nov 2018 19:59:01 +0800 Subject: [PATCH] UefiCpuPkg/SmmCpu: Block access-out only when static paging is used When static paging is disabled, page table for below 4GB is created and page table for above 4GB is created dynamically in page fault handler. Today's implementation only allow SMM access-out to below types of memory address no matter static paging is enabled or not: 1. Reserved, run time and ACPI NVS type 2. MMIO But certain platform feature like RAS may need to access other types of memory from SMM. Today's code blocks these platforms. This patch simplifies the policy to only block when static paging is used so that the static paging can be disabled in these platforms to meet their SMM access-out need. Setting PcdCpuSmmStaticPageTable to FALSE can disable the static paging. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao Signed-off-by: Ruiyu Ni Cc: Eric Dong Reviewed-by: Jiewen Yao Acked-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 5bb7d57238..117502dafa 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -1,7 +1,7 @@ /** @file Page Fault (#PF) handler for X64 processors -Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
This program and the accompanying materials @@ -890,7 +890,7 @@ SmiPFHandler ( CpuDeadLoop (); } - if (IsSmmCommBufferForbiddenAddress (PFAddress)) { + if (mCpuSmmStaticPageTable && IsSmmCommBufferForbiddenAddress (PFAddress)) { DumpCpuContext (InterruptType, SystemContext); DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%lx)!\n", PFAddress)); DEBUG_CODE (