ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3

This is already taken care by Sec when PcdTrustzoneSupport = TRUE.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524

ArmPkg/ArmPkg.dec

@@ -111,24 +111,6 @@
   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 
-  #
-  # ARM Security Extension
-  #
-  
-  # Secure Configuration Register
-  # - BIT0 : NS - Non Secure bit 
-  # - BIT1 : IRQ Handler
-  # - BIT2 : FIQ Handler
-  # - BIT3 : EA - External Abort
-  # - BIT4 : FW - F bit writable
-  # - BIT5 : AW - A bit writable
-  # - BIT6 : nET - Not Early Termination
-  # - BIT7 : SCD - Secure Monitor Call Disable
-  # - BIT8 : HCE - Hyp Call enable
-  # - BIT9 : SIF - Secure Instruction Fetch
-  # 0x31 = NS | EA | FW
-  gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
-
   # System Memory (DRAM): These PCDs define the region of in-built system memory
   # Some platforms can get DRAM extensions, these additional regions will be declared
   # to UEFI by ArmPLatformPlib   
@@ -161,6 +143,24 @@
   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 
 [PcdsFixedAtBuild.ARM]
+  #
+  # ARM Security Extension
+  #
+
+  # Secure Configuration Register
+  # - BIT0 : NS - Non Secure bit
+  # - BIT1 : IRQ Handler
+  # - BIT2 : FIQ Handler
+  # - BIT3 : EA - External Abort
+  # - BIT4 : FW - F bit writable
+  # - BIT5 : AW - A bit writable
+  # - BIT6 : nET - Not Early Termination
+  # - BIT7 : SCD - Secure Monitor Call Disable
+  # - BIT8 : HCE - Hyp Call enable
+  # - BIT9 : SIF - Secure Instruction Fetch
+  # 0x31 = NS | EA | FW
+  gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
+
   # By default we do not do a transition to non-secure mode
   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 
@@ -183,6 +183,28 @@
   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 
 [PcdsFixedAtBuild.AARCH64]
+  #
+  # AArch64 Security Extension
+  #
+
+  # Secure Configuration Register
+  # - BIT0 : NS - Non Secure bit
+  # - BIT1 : IRQ Handler
+  # - BIT2 : FIQ Handler
+  # - BIT3 : EA - External Abort
+  # - BIT4 : FW - F bit writable
+  # - BIT5 : AW - A bit writable
+  # - BIT6 : nET - Not Early Termination
+  # - BIT7 : SCD - Secure Monitor Call Disable
+  # - BIT8 : HCE - Hyp Call enable
+  # - BIT9 : SIF - Secure Instruction Fetch
+  # - BIT10: RW -  Register width control for lower exception levels
+  # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
+  # - BIT12: TWI - Trap WFI
+  # - BIT13: TWE - Trap WFE
+  # 0x501 = NS | HCE | RW
+  gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
+
   # By default we do transition to EL2 non-secure mode with Stack for EL2.
   #        Mode Description              Bits
   # NS EL2 SP2 all interupts disabled =  0x3c9

ArmPlatformPkg/Sec/AArch64/Helper.S

@@ -26,20 +26,6 @@ ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr)
 ASM_GLOBAL ASM_PFX(set_non_secure_mode)
 
 ASM_PFX(SetupExceptionLevel3):
-   mrs    x0, scr_el3            // Read EL3 Secure Configuration Register
-   orr    x0, x0, #1             // EL0 an EL1 cannot access secure memory
-
-   // Send all interrupts to their respective Exception levels for EL3
-   bic    x0, x0, #(1 << 1)      // IRQ
-   bic    x0, x0, #(1 << 2)      // FIQ
-   bic    x0, x0, #(1 << 3)      // Serror and Abort
-   orr    x0, x0, #(1 << 8)      // Enable HVC
-   orr    x0, x0, #(1 << 10)     // Make next level down 64Bit. This is EL2 in the case of the Model.
-                                 // We need a nice way to detect this.
-   msr    scr_el3, x0            // Write back our settings
-
-   msr    cptr_el3, xzr          // Disable copro traps to EL3
-
    // Check for the primary CPU to avoid a race on the distributor registers.
    mrs     x0, mpidr_el1
    tst     x0, #15