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UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA's disabled 

Today's McaInitialize() doesn't check State value before initialize
MCi_CTL and MCi_STATUS.
The patch fixes this issue by only initializing the two kinds of
MSRs when State is enabled.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Ruiyu Ni 2018-02-08 14:43:20 +08:00
parent 7506fe43a1
commit dc7363f848
1 changed files with 17 additions and 15 deletions
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32
UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
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@ -1,7 +1,7 @@
/** @file /** @file
Machine Check features. Machine Check features.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -140,25 +140,27 @@ McaInitialize (
MSR_IA32_MCG_CAP_REGISTER McgCap; MSR_IA32_MCG_CAP_REGISTER McgCap;
UINT32 BankIndex; UINT32 BankIndex;
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); if (State == TRUE) {
for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) { McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
CPU_REGISTER_TABLE_WRITE64 ( for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {
ProcessorNumber,
Msr,
MSR_IA32_MC0_CTL + BankIndex * 4,
MAX_UINT64
);
}
if (PcdGetBool (PcdIsPowerOnReset)) {
for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
MSR_IA32_MC0_STATUS + BankIndex * 4, MSR_IA32_MC0_CTL + BankIndex * 4,
0 MAX_UINT64
); );
} }
if (PcdGetBool (PcdIsPowerOnReset)) {
for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,
MSR_IA32_MC0_STATUS + BankIndex * 4,
0
);
}
}
} }
return RETURN_SUCCESS; return RETURN_SUCCESS;