UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA's disabled
Today's McaInitialize() doesn't check State value before initialize MCi_CTL and MCi_STATUS. The patch fixes this issue by only initializing the two kinds of MSRs when State is enabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
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@ -1,7 +1,7 @@
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/** @file
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/** @file
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Machine Check features.
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Machine Check features.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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which accompanies this distribution. The full text of the license may be found at
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@ -140,25 +140,27 @@ McaInitialize (
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MSR_IA32_MCG_CAP_REGISTER McgCap;
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MSR_IA32_MCG_CAP_REGISTER McgCap;
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UINT32 BankIndex;
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UINT32 BankIndex;
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McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
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if (State == TRUE) {
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for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {
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McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
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CPU_REGISTER_TABLE_WRITE64 (
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for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {
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ProcessorNumber,
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Msr,
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MSR_IA32_MC0_CTL + BankIndex * 4,
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MAX_UINT64
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);
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}
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if (PcdGetBool (PcdIsPowerOnReset)) {
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for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {
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CPU_REGISTER_TABLE_WRITE64 (
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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ProcessorNumber,
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Msr,
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Msr,
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MSR_IA32_MC0_STATUS + BankIndex * 4,
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MSR_IA32_MC0_CTL + BankIndex * 4,
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0
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MAX_UINT64
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);
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);
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}
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}
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if (PcdGetBool (PcdIsPowerOnReset)) {
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for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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MSR_IA32_MC0_STATUS + BankIndex * 4,
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0
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);
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}
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}
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}
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}
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return RETURN_SUCCESS;
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return RETURN_SUCCESS;
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