DynamicTablesPkg: Move LPI info object to Arch Common
Move the LPI info object from Arm Namespace to the Arch Common namespace. Correspondingly also update the following modules to reflect the changes introduced by the move: - SSDT Cpu Topology generator - ConfigurationManagerObjectParser - Dynamic Plat Repo TokenFixer map. Cc: Pierre Gondois <Pierre.Gondois@arm.com> Cc: Yeo Reum Yun <YeoReum.Yun@arm.com> Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com> Cc: Jeshua Smith <jeshuas@nvidia.com> Cc: Jeff Brasen <jbrasen@nvidia.com> Cc: Girish Mahadevan <gmahadevan@nvidia.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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@ -35,6 +35,7 @@ typedef enum ArchCommonObjectID {
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EArchCommonObjDeviceHandleAcpi, ///< 12 - Device Handle Acpi
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EArchCommonObjDeviceHandlePci, ///< 13 - Device Handle Pci
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EArchCommonObjGenericInitiatorAffinityInfo, ///< 14 - Generic Initiator Affinity
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EArchCommonObjLpiInfo, ///< 15 - Lpi Info
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EArchCommonObjMax
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} EARCH_COMMON_OBJECT_ID;
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@ -295,6 +296,69 @@ typedef struct CmArchCommonGenericInitiatorAffinityInfo {
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CM_OBJECT_TOKEN DeviceHandleToken;
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} CM_ARCH_COMMON_GENERIC_INITIATOR_AFFINITY_INFO;
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/** A structure that describes the Lpi information.
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The Low Power Idle states are described in DSDT/SSDT and associated
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to cpus/clusters in the cpu topology.
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ID: EArchCommonObjLpiInfo
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*/
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typedef struct CmArchCommonLpiInfo {
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/** Minimum Residency. Time in microseconds after which a
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state becomes more energy efficient than any shallower state.
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*/
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UINT32 MinResidency;
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/** Worst case time in microseconds from a wake interrupt
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being asserted to the return to a running state
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*/
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UINT32 WorstCaseWakeLatency;
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/** Flags.
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*/
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UINT32 Flags;
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/** Architecture specific context loss flags.
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*/
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UINT32 ArchFlags;
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/** Residency counter frequency in cycles-per-second (Hz).
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*/
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UINT32 ResCntFreq;
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/** Every shallower power state in the parent is also enabled.
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*/
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UINT32 EnableParentState;
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/** The EntryMethod _LPI field can be described as an integer
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or in a Register resource data descriptor.
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If IsInteger is TRUE, the IntegerEntryMethod field is used.
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If IsInteger is FALSE, the RegisterEntryMethod field is used.
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*/
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BOOLEAN IsInteger;
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/** EntryMethod described as an Integer.
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*/
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UINT64 IntegerEntryMethod;
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/** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.
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*/
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EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterEntryMethod;
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/** Residency counter register.
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*/
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EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResidencyCounterRegister;
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/** Usage counter register.
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*/
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EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE UsageCounterRegister;
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/** String representing the Lpi state
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*/
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CHAR8 StateName[16];
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} CM_ARCH_COMMON_LPI_INFO;
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#pragma pack()
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#endif // ARCH_COMMON_NAMESPACE_OBJECTS_H_
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@ -51,18 +51,17 @@ typedef enum ArmObjectID {
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EArmObjProcHierarchyInfo, ///< 20 - Processor Hierarchy Info
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EArmObjCacheInfo, ///< 21 - Cache Info
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EArmObjCmn600Info, ///< 22 - CMN-600 Info
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EArmObjLpiInfo, ///< 23 - Lpi Info
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EArmObjRmr, ///< 24 - Reserved Memory Range Node
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EArmObjMemoryRangeDescriptor, ///< 25 - Memory Range Descriptor
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EArmObjCpcInfo, ///< 26 - Continuous Performance Control Info
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EArmObjPccSubspaceType0Info, ///< 27 - Pcc Subspace Type 0 Info
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EArmObjPccSubspaceType1Info, ///< 28 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType2Info, ///< 29 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType3Info, ///< 30 - Pcc Subspace Type 3 Info
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EArmObjPccSubspaceType4Info, ///< 31 - Pcc Subspace Type 4 Info
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EArmObjPccSubspaceType5Info, ///< 32 - Pcc Subspace Type 5 Info
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EArmObjEtInfo, ///< 33 - Embedded Trace Extension/Module Info
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EArmObjPsdInfo, ///< 34 - P-State Dependency (PSD) Info
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EArmObjRmr, ///< 23 - Reserved Memory Range Node
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EArmObjMemoryRangeDescriptor, ///< 24 - Memory Range Descriptor
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EArmObjCpcInfo, ///< 25 - Continuous Performance Control Info
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EArmObjPccSubspaceType0Info, ///< 26 - Pcc Subspace Type 0 Info
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EArmObjPccSubspaceType1Info, ///< 27 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType2Info, ///< 28 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType3Info, ///< 29 - Pcc Subspace Type 3 Info
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EArmObjPccSubspaceType4Info, ///< 30 - Pcc Subspace Type 4 Info
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EArmObjPccSubspaceType5Info, ///< 31 - Pcc Subspace Type 5 Info
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EArmObjEtInfo, ///< 32 - Embedded Trace Extension/Module Info
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EArmObjPsdInfo, ///< 33 - P-State Dependency (PSD) Info
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EArmObjMax
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} EARM_OBJECT_ID;
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@ -672,7 +671,7 @@ typedef struct CmArmProcHierarchyInfo {
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CM_OBJECT_TOKEN PrivateResourcesArrayToken;
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/// Optional field: Reference Token for the Lpi state of this processor.
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/// Token identifying a CM_ARCH_COMMON_OBJ_REF structure, itself referencing
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/// CM_ARM_LPI_INFO objects.
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/// CM_ARCH_COMMON_LPI_INFO objects.
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CM_OBJECT_TOKEN LpiToken;
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/// Set to TRUE if UID should override index for name and _UID
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/// for processor container nodes and name of processors.
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@ -749,69 +748,6 @@ typedef struct CmArmCmn600Info {
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CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];
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} CM_ARM_CMN_600_INFO;
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/** A structure that describes the Lpi information.
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The Low Power Idle states are described in DSDT/SSDT and associated
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to cpus/clusters in the cpu topology.
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ID: EArmObjLpiInfo
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*/
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typedef struct CmArmLpiInfo {
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/** Minimum Residency. Time in microseconds after which a
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state becomes more energy efficient than any shallower state.
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*/
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UINT32 MinResidency;
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/** Worst case time in microseconds from a wake interrupt
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being asserted to the return to a running state
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*/
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UINT32 WorstCaseWakeLatency;
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/** Flags.
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*/
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UINT32 Flags;
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/** Architecture specific context loss flags.
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*/
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UINT32 ArchFlags;
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/** Residency counter frequency in cycles-per-second (Hz).
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*/
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UINT32 ResCntFreq;
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/** Every shallower power state in the parent is also enabled.
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*/
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UINT32 EnableParentState;
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/** The EntryMethod _LPI field can be described as an integer
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or in a Register resource data descriptor.
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If IsInteger is TRUE, the IntegerEntryMethod field is used.
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If IsInteger is FALSE, the RegisterEntryMethod field is used.
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*/
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BOOLEAN IsInteger;
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/** EntryMethod described as an Integer.
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*/
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UINT64 IntegerEntryMethod;
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/** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.
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*/
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EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterEntryMethod;
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/** Residency counter register.
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*/
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EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResidencyCounterRegister;
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/** Usage counter register.
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*/
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EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE UsageCounterRegister;
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/** String representing the Lpi state
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*/
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CHAR8 StateName[16];
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} CM_ARM_LPI_INFO;
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/** A structure that describes the
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RMR node for the Platform.
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@ -40,7 +40,7 @@ Requirements:
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- EArmObjGicCInfo
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- EArmObjProcHierarchyInfo (OPTIONAL) along with
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- EArchCommonObjCmRef (OPTIONAL)
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- EArmObjLpiInfo (OPTIONAL)
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- EArchCommonObjLpiInfo (OPTIONAL)
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- GetEArmObjEtInfo (OPTIONAL)
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- EArmObjPsdInfo (OPTIONAL)
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*/
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@ -79,9 +79,9 @@ GET_OBJECT_LIST (
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information from the Configuration Manager.
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*/
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GET_OBJECT_LIST (
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EObjNameSpaceArm,
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EArmObjLpiInfo,
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CM_ARM_LPI_INFO
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EObjNameSpaceArchCommon,
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EArchCommonObjLpiInfo,
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CM_ARCH_COMMON_LPI_INFO
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);
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/**
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@ -118,7 +118,7 @@ GET_OBJECT_LIST (
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One entry should be allocated for each CM_ARM_PROC_HIERARCHY_INFO
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structure of the platform. The TokenTable allows to have a mapping:
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Index <-> CM_OBJECT_TOKEN (to CM_ARM_LPI_INFO structures).
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Index <-> CM_OBJECT_TOKEN (to CM_ARCH_COMMON_LPI_INFO structures).
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There will always be less sets of Lpi states (CM_ARCH_COMMON_OBJ_REF)
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than the number of cpus/clusters (CM_ARM_PROC_HIERARCHY_INFO).
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@ -700,7 +700,7 @@ GenerateLpiStates (
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CM_ARCH_COMMON_OBJ_REF *LpiRefInfo;
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UINT32 LpiRefInfoCount;
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UINT32 LpiRefIndex;
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CM_ARM_LPI_INFO *LpiInfo;
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CM_ARCH_COMMON_LPI_INFO *LpiInfo;
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CHAR8 AslName[AML_NAME_SEG_SIZE + 1];
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ASSERT (Generator != NULL);
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@ -739,8 +739,9 @@ GenerateLpiStates (
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}
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for (LpiRefIndex = 0; LpiRefIndex < LpiRefInfoCount; LpiRefIndex++) {
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// For each CM_ARM_LPI_INFO referenced by the token, add an Lpi state.
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Status = GetEArmObjLpiInfo (
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// For each CM_ARCH_COMMON_LPI_INFO referenced by the token,
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// add an Lpi state.
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Status = GetEArchCommonObjLpiInfo (
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CfgMgrProtocol,
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LpiRefInfo[LpiRefIndex].ReferenceToken,
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&LpiInfo,
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@ -70,7 +70,7 @@
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/** A structure used to handle the Lpi structures referencing.
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A CM_ARM_PROC_HIERARCHY_INFO structure references a CM_ARCH_COMMON_OBJ_REF.
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This CM_ARCH_COMMON_OBJ_REF references CM_ARM_LPI_INFO structures.
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This CM_ARCH_COMMON_OBJ_REF references CM_ARCH_COMMON_LPI_INFO structures.
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Example:
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(Cpu0) (Cpu1)
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@ -86,7 +86,7 @@
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| |
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v v
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(A first Lpi state) (A second Lpi state)
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CM_ARM_LPI_INFO[0] CM_ARM_LPI_INFO[1]
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CM_ARCH_COMMON_LPI_INFO[0] CM_ARCH_COMMON_LPI_INFO[1]
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Here, Cpu0 and Cpu1 have the same Lpi states. Both CM_ARM_PROC_HIERARCHY_INFO
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structures reference the same CM_ARCH_COMMON_OBJ_REF. An entry is created in the
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@ -118,7 +118,7 @@
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*/
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typedef struct TokenTable {
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/// TokenTable, a table allowing to map:
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/// Index <-> CM_OBJECT_TOKEN (to CM_ARM_LPI_INFO structures).
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/// Index <-> CM_OBJECT_TOKEN (to CM_ARCH_COMMON_LPI_INFO structures).
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CM_OBJECT_TOKEN *Table;
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/// Last used index of the TokenTable.
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@ -166,18 +166,17 @@ CM_OBJECT_TOKEN_FIXER TokenFixer[EArmObjMax] = {
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TokenFixerNotImplemented, ///< 20 - Processor Hierarchy Info
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TokenFixerNotImplemented, ///< 21 - Cache Info
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NULL, ///< 22 - CMN-600 Info
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NULL, ///< 23 - Lpi Info
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NULL, ///< 24 - Reserved Memory Range Node
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NULL, ///< 25 - Memory Range Descriptor
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NULL, ///< 26 - Continuous Performance Control Info
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NULL, ///< 27 - Pcc Subspace Type 0 Info
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NULL, ///< 23 - Reserved Memory Range Node
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NULL, ///< 24 - Memory Range Descriptor
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NULL, ///< 25 - Continuous Performance Control Info
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NULL, ///< 26 - Pcc Subspace Type 0 Info
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NULL, ///< 27 - Pcc Subspace Type 2 Info
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NULL, ///< 28 - Pcc Subspace Type 2 Info
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NULL, ///< 29 - Pcc Subspace Type 2 Info
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NULL, ///< 30 - Pcc Subspace Type 3 Info
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NULL, ///< 31 - Pcc Subspace Type 4 Info
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NULL, ///< 32 - Pcc Subspace Type 5 Info
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NULL, ///< 33 - Embedded Trace Extension/Module Info
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NULL ///< 34 - P-State Dependency (PSD) Info
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NULL, ///< 29 - Pcc Subspace Type 3 Info
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NULL, ///< 30 - Pcc Subspace Type 4 Info
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NULL, ///< 31 - Pcc Subspace Type 5 Info
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NULL, ///< 32 - Embedded Trace Extension/Module Info
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NULL ///< 33 - P-State Dependency (PSD) Info
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};
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/** CmObj token fixer.
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@ -417,9 +417,9 @@ STATIC CONST CM_OBJ_PARSER AcpiGenericAddressParser[] = {
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{ "Address", 8, "0x%llx", NULL },
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};
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/** A parser for EArmObjLpiInfo.
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/** A parser for EArchCommonObjLpiInfo.
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*/
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STATIC CONST CM_OBJ_PARSER CmArmLpiInfoParser[] = {
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STATIC CONST CM_OBJ_PARSER CmArchCommonLpiInfoParser[] = {
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{ "MinResidency", 4, "0x%x", NULL },
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{ "WorstCaseWakeLatency", 4, "0x%x", NULL },
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{ "Flags", 4, "0x%x", NULL },
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@ -685,6 +685,7 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArchCommonNamespaceObjectParser[] = {
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CM_PARSER_ADD_OBJECT (EArchCommonObjDeviceHandleAcpi, CmArchCommonDeviceHandleAcpiParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjDeviceHandlePci, CmArchCommonDeviceHandlePciParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjGenericInitiatorAffinityInfo,CmArchCommonGenericInitiatorAffinityInfoParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjLpiInfo, CmArchCommonLpiInfoParser),
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CM_PARSER_ADD_OBJECT_RESERVED (EArchCommonObjMax)
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};
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@ -714,7 +715,6 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArmNamespaceObjectParser[] = {
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CM_PARSER_ADD_OBJECT (EArmObjProcHierarchyInfo, CmArmProcHierarchyInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjCacheInfo, CmArmCacheInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjCmn600Info, CmArmCmn600InfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjLpiInfo, CmArmLpiInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjRmr, CmArmRmrInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjMemoryRangeDescriptor, CmArmMemoryRangeDescriptorInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjCpcInfo, CmArmCpcInfoParser),
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@ -463,18 +463,17 @@ The CM_OBJECT_ID type is used to identify the Configuration Manager
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| 20 | Processor Hierarchy Info | Move to Arch Common NS |
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| 21 | Cache Info | Move to Arch Common NS |
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| 22 | CMN 600 Info | |
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| 23 | Low Power Idle State Info | Move to Arch Common NS |
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| 24 | Reserved Memory Range Node | |
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| 25 | Memory Range Descriptor | |
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| 26 | Continuous Performance Control Info | Move to Arch Common NS |
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| 27 | Pcc Subspace Type 0 Info | Move to Arch Common NS |
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| 28 | Pcc Subspace Type 1 Info | Move to Arch Common NS |
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| 29 | Pcc Subspace Type 2 Info | Move to Arch Common NS |
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| 30 | Pcc Subspace Type 3 Info | Move to Arch Common NS |
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| 31 | Pcc Subspace Type 4 Info | Move to Arch Common NS |
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| 32 | Pcc Subspace Type 5 Info | Move to Arch Common NS |
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| 33 | Embedded Trace Extension/Module Info | |
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| 34 | P-State Dependency (PSD) Info | Move to Arch Common NS |
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| 23 | Reserved Memory Range Node | |
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| 24 | Memory Range Descriptor | |
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| 25 | Continuous Performance Control Info | Move to Arch Common NS |
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| 26 | Pcc Subspace Type 0 Info | Move to Arch Common NS |
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| 27 | Pcc Subspace Type 1 Info | Move to Arch Common NS |
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| 28 | Pcc Subspace Type 2 Info | Move to Arch Common NS |
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| 29 | Pcc Subspace Type 3 Info | Move to Arch Common NS |
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| 30 | Pcc Subspace Type 4 Info | Move to Arch Common NS |
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| 31 | Pcc Subspace Type 5 Info | Move to Arch Common NS |
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| 32 | Embedded Trace Extension/Module Info | |
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| 33 | P-State Dependency (PSD) Info | Move to Arch Common NS |
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| `*` | All other values are reserved. | |
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#### Object ID's in the Arch Common Namespace:
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@ -496,4 +495,5 @@ The CM_OBJECT_ID type is used to identify the Configuration Manager
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| 12 | Device Handle Acpi | |
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| 13 | Device Handle PCI | |
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| 14 | Generic Initiator Affinity Info | |
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| 15 | Low Power Idle State Info | |
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| `*` | All other values are reserved. | |
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