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https://gitlab.com/qemu-project/edk2.git
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2d2642f483
When re-entering EDK2 from a high level OS such as Linux, the GICv3 may be configured to use split priority drop and deactivate (EOImode == 1), whereas EDK2's GICv3 driver assumes the default setting of EOImode == 0. So clear the EOImode bit explicitly when taking control of the GIC. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
97 lines
2.2 KiB
ArmAsm
97 lines
2.2 KiB
ArmAsm
#
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# Copyright (c) 2014, ARM Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#
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#include <AsmMacroLib.h>
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#include <Library/ArmLib.h>
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// For the moment we assume this will run in SVC mode on ARMv7
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//UINT32
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//EFIAPI
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//ArmGicGetControlSystemRegisterEnable (
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// VOID
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// );
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ASM_FUNC(ArmGicV3GetControlSystemRegisterEnable)
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mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
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bx lr
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//VOID
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//EFIAPI
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//ArmGicSetControlSystemRegisterEnable (
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// IN UINT32 ControlSystemRegisterEnable
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// );
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ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable)
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mcr p15, 0, r0, c12, c12, 5 // ICC_SRE
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isb
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bx lr
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//VOID
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//ArmGicV3EnableInterruptInterface (
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// VOID
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// );
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ASM_FUNC(ArmGicV3EnableInterruptInterface)
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mov r0, #1
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mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
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bx lr
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//VOID
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//ArmGicV3DisableInterruptInterface (
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// VOID
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// );
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ASM_FUNC(ArmGicV3DisableInterruptInterface)
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mov r0, #0
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mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
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bx lr
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//VOID
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//ArmGicV3EndOfInterrupt (
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// IN UINTN InterruptId
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// );
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ASM_FUNC(ArmGicV3EndOfInterrupt)
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mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1
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bx lr
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//UINTN
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//ArmGicV3AcknowledgeInterrupt (
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// VOID
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// );
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ASM_FUNC(ArmGicV3AcknowledgeInterrupt)
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mrc p15, 0, r0, c12, c12, 0 //ICC_IAR1
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bx lr
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//VOID
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//ArmGicV3SetPriorityMask (
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// IN UINTN Priority
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// );
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ASM_FUNC(ArmGicV3SetPriorityMask)
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mcr p15, 0, r0, c4, c6, 0 //ICC_PMR
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bx lr
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//VOID
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//ArmGicV3SetBinaryPointer (
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// IN UINTN BinaryPoint
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// );
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ASM_FUNC(ArmGicV3SetBinaryPointer)
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mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1
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bx lr
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//UINTN
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//ArmGicV3GetControlRegister(
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// VOID
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// );
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ASM_FUNC(ArmGicV3GetControlRegister)
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mrc p15, 0, r0, c12, c12, 4 //ICC_CTLR
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bx lr
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//VOID
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//ArmGicV3SetControlRegister(
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// IN UINTN Value
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// );
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ASM_FUNC(ArmGicV3SetControlRegister)
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mcr p15, 0, r0, c12, c12, 4 //ICC_CTLR
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bx lr
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