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https://gitlab.com/qemu-project/openbios.git
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Eliminate M4 macros
git-svn-id: svn://coreboot.org/openbios/openbios-devel@266 f158a5a8-5612-0410-a976-696ce0be7e32
This commit is contained in:
Blue Swirl
@@ -18,13 +18,6 @@
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#ifndef _H_ASMDEFS
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#define _H_ASMDEFS
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#include "openbios/asm.m4"
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#ifndef __ASSEMBLY__
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#error This file is only to be included from assembler code!
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#endif
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/************************************************************************/
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/* High/low halfword compatibility macros */
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/************************************************************************/
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@@ -38,325 +31,51 @@
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#define HI(v) hi16(v)
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#define LO(v) lo16(v)
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/************************************************************************/
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/* Register name prefix */
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/************************************************************************/
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/* from Linux: include/asm-powerpc/ppc_asm.h */
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/*
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* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
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*/
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#ifdef __linux__
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define([rPREFIX], [])
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define([fPREFIX], [])
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define([srPREFIX], [])
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#else
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define([rPREFIX], [r])
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define([fPREFIX], [f])
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define([srPREFIX], [sr])
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/* frN -> fN */
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mFORLOOP([i],0,31,[define(fr[]i,f[]i)])
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#endif
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/* General Purpose Registers (GPRs) */
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/************************************************************************/
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/* Macros and definitions */
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/************************************************************************/
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#define r0 0
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#define r1 1
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#define r2 2
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#define r3 3
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#define r4 4
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#define r5 5
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#define r6 6
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#define r7 7
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#define r8 8
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#define r9 9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r24 24
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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#ifdef __darwin__
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#define balign_4 .align 2,0
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#define balign_8 .align 3,0
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#define balign_16 .align 4,0
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#define balign_32 .align 5,0
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#endif
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#ifdef __linux__
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#define balign_4 .balign 4,0
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#define balign_8 .balign 8,0
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#define balign_16 .balign 16,0
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#define balign_32 .balign 32,0
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#endif
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MACRO(LOADVAR, [dreg, variable], [
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lis _dreg,HA(_variable)
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lwz _dreg,LO(_variable)(_dreg)
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])
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MACRO(LOADI, [dreg, addr], [
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lis _dreg,HA(_addr)
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addi _dreg,_dreg,LO(_addr)
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])
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MACRO(LOAD_GPR_RANGE, [start, endx, offs, base], [
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mFORLOOP([i],0,31,[ .if (i >= _start) & (i <= _endx)
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lwz rPREFIX[]i,_offs+i[]*4(_base)
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.endif
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])])
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MACRO(STORE_GPR_RANGE, [start, endx, offs, base], [
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mFORLOOP([i],0,31,[ .if (i >= _start) & (i <= _endx)
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stw rPREFIX[]i,_offs+i[]*4(_base)
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.endif
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])])
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MACRO(LOAD_FPR_RANGE, [start, endx, offs, base], [
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mFORLOOP([i],0,31,[ .if (i >= _start) & (i <= _endx)
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lfd fPREFIX[]i,_offs+i[]*8(_base)
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.endif
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])])
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MACRO(STORE_FPR_RANGE, [start, endx, offs, base], [
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mFORLOOP([i],0,31,[ .if (i >= _start) & (i <= _endx)
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stfd fPREFIX[]i,_offs+i[]*8(_base)
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.endif
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])])
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/************************************************************************/
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/* FPU load/save macros */
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/************************************************************************/
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// The FPU macros are used both in the kernel and in
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// mainloop_asm.h.
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MACRO(xFPR_LOAD_RANGE, [from, to, mbase], [
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LOAD_FPR_RANGE _from,_to,xFPR_BASE,_mbase
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])
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MACRO(xFPR_SAVE_RANGE, [from, to, mbase], [
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STORE_FPR_RANGE _from,_to,xFPR_BASE,_mbase
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])
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// The low half of the fpu is fr0-fr12. I.e. the FPU registers
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// that might be overwritten when a function call is taken
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// (fr13 and fpscr are treated specially).
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MACRO(xLOAD_LOW_FPU, [mbase], [
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xFPR_LOAD_RANGE 0,12,_mbase
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])
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MACRO(xLOAD_TOPHALF_FPU, [mbase], [
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xFPR_LOAD_RANGE 14,31,_mbase
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])
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MACRO(xLOAD_FULL_FPU, [mbase], [
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xLOAD_LOW_FPU _mbase
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xLOAD_TOPHALF_FPU _mbase
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])
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MACRO(xSAVE_LOW_FPU, [mbase], [
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xFPR_SAVE_RANGE 0,12,_mbase
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])
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MACRO(xSAVE_TOPHALF_FPU, [mbase], [
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xFPR_SAVE_RANGE 14,31,_mbase
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])
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MACRO(xSAVE_FULL_FPU, [mbase], [
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xSAVE_LOW_FPU _mbase
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xSAVE_TOPHALF_FPU _mbase
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])
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/************************************************************************/
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/* GPR load/save macros */
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/************************************************************************/
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MACRO(xGPR_SAVE_RANGE, [from, to, mbase], [
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STORE_GPR_RANGE _from, _to, xGPR0, _mbase
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])
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MACRO(xGPR_LOAD_RANGE, [from, to, mbase], [
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LOAD_GPR_RANGE _from, _to, xGPR0, _mbase
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])
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/************************************************************************/
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/* AltiVec */
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/************************************************************************/
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#ifdef __linux__
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define(vPREFIX,[])
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#ifndef HAVE_ALTIVEC
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#define VEC_OPCODE( op1,op2,A,B,C ) \
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.long (((op1) << (32-6)) | (op2) | ((A) << (32-11)) | ((B) << (32-16)) | ((C) << (32-21))) ;
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#define __stvx( vS,rA,rB ) VEC_OPCODE( 31,0x1ce,vS,rA,rB )
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#define __lvx( vD,rA,rB ) VEC_OPCODE( 31,0xce, vD,rA,rB )
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#define __mfvscr( vD ) VEC_OPCODE( 4,1540,vD,0,0 )
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#define __mtvscr( vB ) VEC_OPCODE( 4,1604,0,0,vB )
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#define __stvewx( vS,rA,rB ) VEC_OPCODE( 31,(199<<1), vS,rA,rB )
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mFORLOOP([i],0,31,[define(v[]i,[]i)])
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MACRO(stvx, [vS,rA,rB], [ __stvx( _vS,_rA,_rB ) ; ])
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MACRO(lvx, [vD,rA,rB], [ __lvx( _vD,_rA,_rB ) ; ])
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MACRO(mfvscr, [vD], [ __mfvscr( _vD ) ; ])
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MACRO(mtvscr, [vB], [ __mtvscr( _vB ) ; ])
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MACRO(stvewx, [vS,rA,rB], [ __stvewx( _vS,_rA,_rB ) ; ])
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#endif
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#else /* __linux__ */
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define(vPREFIX,[v])
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#endif /* __linux__ */
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// NOTE: Writing to VSCR won't cause exceptions (this
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// is different compared to FPSCR).
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MACRO(xVEC_SAVE, [mbase, scr], [
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addi _scr,_mbase,xVEC_BASE
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mFORLOOP([i],0,31,[
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stvx vPREFIX[]i,0,_scr
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addi _scr,_scr,16
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])
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addi _scr,_mbase,xVSCR-12
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mfvscr v0
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stvx v0,0,_scr
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addi _scr,_mbase,xVEC0
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lvx v0,0,_scr
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mfspr _scr,S_VRSAVE
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stw _scr,xVRSAVE(_mbase)
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])
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MACRO(xVEC_LOAD, [mbase, scr], [
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addi _scr,_mbase,xVSCR-12
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lvx v0,0,_scr
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mtvscr v0
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addi _scr,_mbase,xVEC_BASE
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mFORLOOP([i],0,31,[
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lvx vPREFIX[]i,0,_scr
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addi _scr,_scr,16
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])
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lwz _scr,xVRSAVE(_mbase)
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mtspr S_VRSAVE,_scr
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])
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/************************************************************************/
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/* Instructions */
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/************************************************************************/
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#ifdef __darwin__
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MACRO(mtsprg0, [reg], [mtspr SPRG0,_reg] )
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MACRO(mtsprg1, [reg], [mtspr SPRG1,_reg] )
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MACRO(mtsprg2, [reg], [mtspr SPRG2,_reg] )
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MACRO(mtsprg3, [reg], [mtspr SPRG3,_reg] )
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MACRO(mfsprg0, [reg], [mfspr _reg,SPRG0] )
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MACRO(mfsprg1, [reg], [mfspr _reg,SPRG1] )
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MACRO(mfsprg2, [reg], [mfspr _reg,SPRG2] )
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MACRO(mfsprg3, [reg], [mfspr _reg,SPRG3] )
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#endif
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/************************************************************************/
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/* Register names */
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/************************************************************************/
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#ifdef __darwin__
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/* These symbols are not defined under Darwin */
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#define cr0 0
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#define cr1 1
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#define cr2 2
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#define cr3 3
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#define cr4 4
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#define cr5 5
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#define cr6 6
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#define cr7 7
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#define cr8 8
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#define lt 0 /* Less than */
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#define gt 1 /* Greater than */
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#define eq 2 /* Equal */
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#define so 3 /* Summary Overflow */
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#define un 3 /* Unordered (after floating point) */
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#endif
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/* FPU register names (to be used as macro arguments) */
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#define FR0 0
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#define FR1 1
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#define FR2 2
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#define FR3 3
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#define FR4 4
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#define FR5 5
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#define FR6 6
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#define FR7 7
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#define FR8 8
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#define FR9 9
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#define FR10 10
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#define FR11 11
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#define FR12 12
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#define FR13 13
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#define FR14 14
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#define FR15 15
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#define FR16 16
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#define FR17 17
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#define FR18 18
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#define FR19 19
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#define FR20 20
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#define FR21 21
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#define FR22 22
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#define FR23 23
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#define FR24 24
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#define FR25 25
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#define FR26 26
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#define FR27 27
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#define FR28 28
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#define FR29 29
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#define FR30 30
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#define FR31 31
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/* GPR register names (to be used as macro arguments) */
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#define R0 0
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#define R1 1
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#define R2 2
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#define R3 3
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#define R4 4
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#define R5 5
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#define R6 6
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#define R7 7
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#define R8 8
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#define R9 9
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#define R10 10
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#define R11 11
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#define R12 12
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#define R13 13
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#define R14 14
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#define R15 15
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#define R16 16
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#define R17 17
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#define R18 18
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#define R19 19
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#define R20 20
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#define R21 21
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#define R22 22
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#define R23 23
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#define R24 24
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#define R25 25
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#define R26 26
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#define R27 27
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#define R28 28
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#define R29 29
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#define R30 30
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#define R31 31
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#ifndef __darwin__
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/* GPR register names, rN -> N, frN -> N, vN -> N */
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mFORLOOP([i],0,31,[define(r[]i,[]i)])
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mFORLOOP([i],0,31,[define(fr[]i,[]i)])
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mFORLOOP([i],0,31,[define(v[]i,[]i)])
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#endif /* __darwin__ */
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/************************************************************************/
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/* useful macros */
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/************************************************************************/
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MACRO(ori_, [reg1, reg2, value], [
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.if (_value & 0xffff)
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ori _reg1, _reg2, (_value) & 0xffff
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.endif
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.if (_value & ~0xffff)
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oris _reg1, _reg2, (_value) >> 16
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.endif
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])
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/************************************************************************/
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/* MISC */
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/************************************************************************/
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#ifdef __linux__
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#ifndef __darwin__
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#define GLOBL( name ) .globl name ; name
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#define EXTERN( name ) name
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#else
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