mirror of
https://gitlab.com/qemu-project/openbios.git
synced 2024-02-13 08:34:06 +08:00
Eliminate M4 macros
git-svn-id: svn://coreboot.org/openbios/openbios-devel@266 f158a5a8-5612-0410-a976-696ce0be7e32
This commit is contained in:
Blue Swirl
@@ -102,9 +102,7 @@
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<library name="briq" target="target" type="static" condition="BRIQ">
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<object source="misc.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<object source="ofmem.c"/>
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<object source="briq/briq.c" flags="-Iarch/ppc"/>
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@@ -119,9 +117,7 @@
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<library name="pearpc" target="target" type="static" condition="PEARPC">
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<object source="misc.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<object source="ofmem.c"/>
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<object source="pearpc/pearpc.c" flags="-Iarch/ppc"/>
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@@ -138,9 +134,7 @@
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<library name="qemu" target="target" type="static" condition="QEMU">
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<object source="misc.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<object source="ofmem.c"/>
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<object source="qemu/qemu.c" flags="-Iarch/ppc"/>
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@@ -157,9 +151,7 @@
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<library name="mol" target="target" type="static" condition="MOL">
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<object source="misc.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<object source="ofmem.c"/>
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<object source="mol/init.c" flags="-Iarch/ppc"/>
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@@ -184,15 +176,11 @@
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</rule>
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<object source="start.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<object source="timebase.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<external-object source="libbriq.a"/>
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<external-object source="libbootstrap.a"/>
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@@ -212,15 +200,11 @@
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</rule>
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<object source="start.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<object source="timebase.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<external-object source="libpearpc.a"/>
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<external-object source="libbootstrap.a"/>
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@@ -239,15 +223,11 @@
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</rule>
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<object source="start.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<object source="timebase.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<external-object source="libqemu.a"/>
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<external-object source="libbootstrap.a"/>
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@@ -270,9 +250,7 @@
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</rule>
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<object source="start.S">
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<rule><![CDATA[
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$(CPP) -D__ASSEMBLY__ $(INCLUDES) $< | $(M4) -s $(M4_NO_GNU) | tr ';' '\n' > $@.s
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$(AS) $@.s $(AS_FLAGS) -o $@
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]]></rule>
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$(CC) $$EXTRACFLAGS $(AS_FLAGS) $(CFLAGS) $(INCLUDES) -c -o $@ $^]]></rule>
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</object>
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<external-object source="libmol.a"/>
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<external-object source="libbootstrap.a"/>
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@@ -20,7 +20,6 @@
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*
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*/
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changequote([[[[[,]]]]]) [[[[[ /* shield includes from m4-expansion */
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#include "asm/asmdefs.h"
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#include "asm/processor.h"
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103
arch/ppc/start.S
103
arch/ppc/start.S
@@ -14,7 +14,6 @@
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*
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*/
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changequote([[[[[,]]]]]) [[[[[ /* shield includes from m4-expansion */
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#include "asm/asmdefs.h"
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#include "asm/processor.h"
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#include "osi.h"
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@@ -26,38 +25,37 @@ changequote([[[[[,]]]]]) [[[[[ /* shield includes from m4-expansion */
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#define ILLEGAL_VECTOR( v ) .org __vectors + v ; bl trap_error ;
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#define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v
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MACRO(EXCEPTION_PREAMBLE, [
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mtsprg1 r1 // scratch
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mfsprg0 r1 // exception stack in sprg0
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addi r1,r1,-80 // push exception frame
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stw r0,0(r1) // save r0
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mfsprg1 r0
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stw r0,4(r1) // save r1
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stw r2,8(r1) // save r2
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stw r3,12(r1) // save r3
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stw r4,16(r1)
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stw r5,20(r1)
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stw r6,24(r1)
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stw r7,28(r1)
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stw r8,32(r1)
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stw r9,36(r1)
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stw r10,40(r1)
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stw r11,44(r1)
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stw r12,48(r1)
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mflr r0
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stw r0,52(r1)
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mfcr r0
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stw r0,56(r1)
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mfctr r0
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stw r0,60(r1)
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mfxer r0
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stw r0,64(r1)
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// 76(r1) unused
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addi r1,r1,-16 // call conventions uses 0(r1) and 4(r1)...
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])
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#define EXCEPTION_PREAMBLE \
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mtsprg1 r1 ; /* scratch */ \
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mfsprg0 r1 ; /* exception stack in sprg0 */ \
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addi r1,r1,-80 ; /* push exception frame */ \
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\
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stw r0,0(r1) ; /* save r0 */ \
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mfsprg1 r0 ; \
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stw r0,4(r1) ; /* save r1 */ \
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stw r2,8(r1) ; /* save r2 */ \
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stw r3,12(r1) ; /* save r3 */ \
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stw r4,16(r1) ; \
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stw r5,20(r1) ; \
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stw r6,24(r1) ; \
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stw r7,28(r1) ; \
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stw r8,32(r1) ; \
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stw r9,36(r1) ; \
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stw r10,40(r1) ; \
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stw r11,44(r1) ; \
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stw r12,48(r1) ; \
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\
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mflr r0 ; \
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stw r0,52(r1) ; \
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mfcr r0 ; \
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stw r0,56(r1) ; \
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mfctr r0 ; \
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stw r0,60(r1) ; \
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mfxer r0 ; \
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stw r0,64(r1) ; \
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\
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/* 76(r1) unused */ \
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addi r1,r1,-16 ; /* call conventions uses 0(r1) and 4(r1)... */
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/************************************************************************/
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@@ -86,12 +84,15 @@ GLOBL(_start):
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li r0,0
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mtmsr r0
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LOADI r1,estack
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lis r1,HA(estack)
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addi r1,r1,LO(estack)
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mtsprg0 r1 // setup exception stack
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LOADI r1,stack
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lis r1,HA(stack)
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addi r1,r1,LO(stack)
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// copy exception vectors
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LOADI r3,__vectors
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lis r3,HA(__vectors)
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addi r3,r3,LO(__vectors)
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li r4,0
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li r5,__vectors_end - __vectors + 16
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rlwinm r5,r5,0,0,28
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@@ -136,17 +137,21 @@ GLOBL(call_elf):
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stwu r1,-16(r1)
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stw r0,20(r1)
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mtlr r3
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LOADI r8,saved_stack // save our stack pointer
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lis r8,HA(saved_stack)
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addi r8,r8,LO(saved_stack) // save our stack pointer
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stw r1,0(r8)
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LOADI r1,client_stack
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LOADI r5,of_client_callback // r5 = callback
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lis r1,HA(client_stack)
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addi r1,r1,LO(client_stack)
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lis r5,HA(of_client_callback)
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addi r5,r5,LO(of_client_callback) // r5 = callback
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li r6,0 // r6 = address of client program arguments (unused)
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li r7,0 // r7 = length of client program arguments (unused)
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li r0,MSR_FP | MSR_ME | MSR_DR | MSR_IR
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mtmsr r0
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blrl
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LOADI r8,saved_stack // restore stack pointer
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lis r8,HA(saved_stack)
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addi r8,r8,LO(saved_stack) // restore stack pointer
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mr r1,r8
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lwz r0,20(r1)
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mtlr r0
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@@ -156,7 +161,8 @@ GLOBL(call_elf):
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blr
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GLOBL(of_client_callback):
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LOADI r4,saved_stack
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lis r4,HA(saved_stack)
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addi r4,r4,LO(saved_stack)
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lwz r4,0(r4)
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stwu r4,-32(r4)
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mflr r5
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@@ -191,8 +197,10 @@ GLOBL(of_rtas_start):
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/* r3 = argument buffer, r4 = of_rtas_start */
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/* according to the CHRP standard, cr must be preserved (cr0/cr1 too?) */
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mr r6,r3
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LOADI r3,OSI_SC_MAGIC_R3
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LOADI r4,OSI_SC_MAGIC_R4
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lis r3,HA(OSI_SC_MAGIC_R3)
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addi r3,r3,LO(OSI_SC_MAGIC_R3)
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lis r4,HA(OSI_SC_MAGIC_R4)
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addi r4,r4,LO(OSI_SC_MAGIC_R4)
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li r5,OSI_OF_RTAS
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sc
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blr
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@@ -203,7 +211,8 @@ GLOBL(of_rtas_end):
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GLOBL(nw_dec_calibration):
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.long 0
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GLOBL(timer_calib_start):
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LOADI r3,nw_dec_calibration
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lis r3,HA(nw_dec_calibration)
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addi r3,r3,LO(nw_dec_calibration)
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lwz r3,0(r3)
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blr
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GLOBL(timer_calib_end):
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@@ -254,14 +263,16 @@ ILLEGAL_VECTOR( 0x200 )
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VECTOR( 0x300, "DSI" ):
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EXCEPTION_PREAMBLE
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LOADI r3,dsi_exception
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lis r3,HA(dsi_exception)
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addi r3,r3,LO(dsi_exception)
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mtctr r3
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bctrl
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b exception_return
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VECTOR( 0x400, "ISI" ):
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EXCEPTION_PREAMBLE
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LOADI r3,isi_exception
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lis r3,HA(isi_exception)
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addi r3,r3,LO(isi_exception)
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mtctr r3
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bctrl
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b exception_return
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@@ -1,4 +1,3 @@
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changequote([[[[[,]]]]]) [[[[[ /* shield includes from m4-expansion */
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#include "asm/asmdefs.h"
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#include "asm/processor.h"
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@@ -18,13 +18,6 @@
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#ifndef _H_ASMDEFS
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#define _H_ASMDEFS
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#include "openbios/asm.m4"
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#ifndef __ASSEMBLY__
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#error This file is only to be included from assembler code!
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#endif
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/************************************************************************/
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/* High/low halfword compatibility macros */
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/************************************************************************/
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@@ -38,325 +31,51 @@
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#define HI(v) hi16(v)
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#define LO(v) lo16(v)
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/* from Linux: include/asm-powerpc/ppc_asm.h */
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/*
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* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
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*/
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/************************************************************************/
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/* Register name prefix */
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/************************************************************************/
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/* General Purpose Registers (GPRs) */
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#ifdef __linux__
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define([rPREFIX], [])
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define([fPREFIX], [])
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define([srPREFIX], [])
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#else
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define([rPREFIX], [r])
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define([fPREFIX], [f])
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define([srPREFIX], [sr])
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/* frN -> fN */
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mFORLOOP([i],0,31,[define(fr[]i,f[]i)])
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#endif
|
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|
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/************************************************************************/
|
||||
/* Macros and definitions */
|
||||
/************************************************************************/
|
||||
|
||||
#ifdef __darwin__
|
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#define balign_4 .align 2,0
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#define balign_8 .align 3,0
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#define balign_16 .align 4,0
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||||
#define balign_32 .align 5,0
|
||||
#endif
|
||||
|
||||
#ifdef __linux__
|
||||
#define balign_4 .balign 4,0
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||||
#define balign_8 .balign 8,0
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#define balign_16 .balign 16,0
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#define balign_32 .balign 32,0
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#endif
|
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|
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MACRO(LOADVAR, [dreg, variable], [
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lis _dreg,HA(_variable)
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lwz _dreg,LO(_variable)(_dreg)
|
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])
|
||||
|
||||
MACRO(LOADI, [dreg, addr], [
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||||
lis _dreg,HA(_addr)
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||||
addi _dreg,_dreg,LO(_addr)
|
||||
])
|
||||
|
||||
MACRO(LOAD_GPR_RANGE, [start, endx, offs, base], [
|
||||
mFORLOOP([i],0,31,[ .if (i >= _start) & (i <= _endx)
|
||||
lwz rPREFIX[]i,_offs+i[]*4(_base)
|
||||
.endif
|
||||
])])
|
||||
|
||||
MACRO(STORE_GPR_RANGE, [start, endx, offs, base], [
|
||||
mFORLOOP([i],0,31,[ .if (i >= _start) & (i <= _endx)
|
||||
stw rPREFIX[]i,_offs+i[]*4(_base)
|
||||
.endif
|
||||
])])
|
||||
|
||||
MACRO(LOAD_FPR_RANGE, [start, endx, offs, base], [
|
||||
mFORLOOP([i],0,31,[ .if (i >= _start) & (i <= _endx)
|
||||
lfd fPREFIX[]i,_offs+i[]*8(_base)
|
||||
.endif
|
||||
])])
|
||||
|
||||
MACRO(STORE_FPR_RANGE, [start, endx, offs, base], [
|
||||
mFORLOOP([i],0,31,[ .if (i >= _start) & (i <= _endx)
|
||||
stfd fPREFIX[]i,_offs+i[]*8(_base)
|
||||
.endif
|
||||
])])
|
||||
|
||||
/************************************************************************/
|
||||
/* FPU load/save macros */
|
||||
/************************************************************************/
|
||||
|
||||
// The FPU macros are used both in the kernel and in
|
||||
// mainloop_asm.h.
|
||||
|
||||
MACRO(xFPR_LOAD_RANGE, [from, to, mbase], [
|
||||
LOAD_FPR_RANGE _from,_to,xFPR_BASE,_mbase
|
||||
])
|
||||
MACRO(xFPR_SAVE_RANGE, [from, to, mbase], [
|
||||
STORE_FPR_RANGE _from,_to,xFPR_BASE,_mbase
|
||||
])
|
||||
// The low half of the fpu is fr0-fr12. I.e. the FPU registers
|
||||
// that might be overwritten when a function call is taken
|
||||
// (fr13 and fpscr are treated specially).
|
||||
|
||||
MACRO(xLOAD_LOW_FPU, [mbase], [
|
||||
xFPR_LOAD_RANGE 0,12,_mbase
|
||||
])
|
||||
|
||||
MACRO(xLOAD_TOPHALF_FPU, [mbase], [
|
||||
xFPR_LOAD_RANGE 14,31,_mbase
|
||||
])
|
||||
MACRO(xLOAD_FULL_FPU, [mbase], [
|
||||
xLOAD_LOW_FPU _mbase
|
||||
xLOAD_TOPHALF_FPU _mbase
|
||||
])
|
||||
|
||||
MACRO(xSAVE_LOW_FPU, [mbase], [
|
||||
xFPR_SAVE_RANGE 0,12,_mbase
|
||||
])
|
||||
MACRO(xSAVE_TOPHALF_FPU, [mbase], [
|
||||
xFPR_SAVE_RANGE 14,31,_mbase
|
||||
])
|
||||
MACRO(xSAVE_FULL_FPU, [mbase], [
|
||||
xSAVE_LOW_FPU _mbase
|
||||
xSAVE_TOPHALF_FPU _mbase
|
||||
])
|
||||
|
||||
|
||||
/************************************************************************/
|
||||
/* GPR load/save macros */
|
||||
/************************************************************************/
|
||||
|
||||
MACRO(xGPR_SAVE_RANGE, [from, to, mbase], [
|
||||
STORE_GPR_RANGE _from, _to, xGPR0, _mbase
|
||||
])
|
||||
|
||||
MACRO(xGPR_LOAD_RANGE, [from, to, mbase], [
|
||||
LOAD_GPR_RANGE _from, _to, xGPR0, _mbase
|
||||
])
|
||||
|
||||
|
||||
/************************************************************************/
|
||||
/* AltiVec */
|
||||
/************************************************************************/
|
||||
|
||||
#ifdef __linux__
|
||||
|
||||
define(vPREFIX,[])
|
||||
|
||||
#ifndef HAVE_ALTIVEC
|
||||
#define VEC_OPCODE( op1,op2,A,B,C ) \
|
||||
.long (((op1) << (32-6)) | (op2) | ((A) << (32-11)) | ((B) << (32-16)) | ((C) << (32-21))) ;
|
||||
|
||||
#define __stvx( vS,rA,rB ) VEC_OPCODE( 31,0x1ce,vS,rA,rB )
|
||||
#define __lvx( vD,rA,rB ) VEC_OPCODE( 31,0xce, vD,rA,rB )
|
||||
#define __mfvscr( vD ) VEC_OPCODE( 4,1540,vD,0,0 )
|
||||
#define __mtvscr( vB ) VEC_OPCODE( 4,1604,0,0,vB )
|
||||
#define __stvewx( vS,rA,rB ) VEC_OPCODE( 31,(199<<1), vS,rA,rB )
|
||||
|
||||
mFORLOOP([i],0,31,[define(v[]i,[]i)])
|
||||
MACRO(stvx, [vS,rA,rB], [ __stvx( _vS,_rA,_rB ) ; ])
|
||||
MACRO(lvx, [vD,rA,rB], [ __lvx( _vD,_rA,_rB ) ; ])
|
||||
MACRO(mfvscr, [vD], [ __mfvscr( _vD ) ; ])
|
||||
MACRO(mtvscr, [vB], [ __mtvscr( _vB ) ; ])
|
||||
MACRO(stvewx, [vS,rA,rB], [ __stvewx( _vS,_rA,_rB ) ; ])
|
||||
#endif
|
||||
#else /* __linux__ */
|
||||
|
||||
define(vPREFIX,[v])
|
||||
|
||||
#endif /* __linux__ */
|
||||
|
||||
|
||||
// NOTE: Writing to VSCR won't cause exceptions (this
|
||||
// is different compared to FPSCR).
|
||||
|
||||
MACRO(xVEC_SAVE, [mbase, scr], [
|
||||
addi _scr,_mbase,xVEC_BASE
|
||||
mFORLOOP([i],0,31,[
|
||||
stvx vPREFIX[]i,0,_scr
|
||||
addi _scr,_scr,16
|
||||
])
|
||||
addi _scr,_mbase,xVSCR-12
|
||||
mfvscr v0
|
||||
stvx v0,0,_scr
|
||||
addi _scr,_mbase,xVEC0
|
||||
lvx v0,0,_scr
|
||||
mfspr _scr,S_VRSAVE
|
||||
stw _scr,xVRSAVE(_mbase)
|
||||
])
|
||||
|
||||
MACRO(xVEC_LOAD, [mbase, scr], [
|
||||
addi _scr,_mbase,xVSCR-12
|
||||
lvx v0,0,_scr
|
||||
mtvscr v0
|
||||
addi _scr,_mbase,xVEC_BASE
|
||||
mFORLOOP([i],0,31,[
|
||||
lvx vPREFIX[]i,0,_scr
|
||||
addi _scr,_scr,16
|
||||
])
|
||||
lwz _scr,xVRSAVE(_mbase)
|
||||
mtspr S_VRSAVE,_scr
|
||||
])
|
||||
|
||||
/************************************************************************/
|
||||
/* Instructions */
|
||||
/************************************************************************/
|
||||
|
||||
#ifdef __darwin__
|
||||
MACRO(mtsprg0, [reg], [mtspr SPRG0,_reg] )
|
||||
MACRO(mtsprg1, [reg], [mtspr SPRG1,_reg] )
|
||||
MACRO(mtsprg2, [reg], [mtspr SPRG2,_reg] )
|
||||
MACRO(mtsprg3, [reg], [mtspr SPRG3,_reg] )
|
||||
MACRO(mfsprg0, [reg], [mfspr _reg,SPRG0] )
|
||||
MACRO(mfsprg1, [reg], [mfspr _reg,SPRG1] )
|
||||
MACRO(mfsprg2, [reg], [mfspr _reg,SPRG2] )
|
||||
MACRO(mfsprg3, [reg], [mfspr _reg,SPRG3] )
|
||||
#endif
|
||||
|
||||
/************************************************************************/
|
||||
/* Register names */
|
||||
/************************************************************************/
|
||||
|
||||
#ifdef __darwin__
|
||||
/* These symbols are not defined under Darwin */
|
||||
#define cr0 0
|
||||
#define cr1 1
|
||||
#define cr2 2
|
||||
#define cr3 3
|
||||
#define cr4 4
|
||||
#define cr5 5
|
||||
#define cr6 6
|
||||
#define cr7 7
|
||||
#define cr8 8
|
||||
#define lt 0 /* Less than */
|
||||
#define gt 1 /* Greater than */
|
||||
#define eq 2 /* Equal */
|
||||
#define so 3 /* Summary Overflow */
|
||||
#define un 3 /* Unordered (after floating point) */
|
||||
#endif
|
||||
|
||||
/* FPU register names (to be used as macro arguments) */
|
||||
#define FR0 0
|
||||
#define FR1 1
|
||||
#define FR2 2
|
||||
#define FR3 3
|
||||
#define FR4 4
|
||||
#define FR5 5
|
||||
#define FR6 6
|
||||
#define FR7 7
|
||||
#define FR8 8
|
||||
#define FR9 9
|
||||
#define FR10 10
|
||||
#define FR11 11
|
||||
#define FR12 12
|
||||
#define FR13 13
|
||||
#define FR14 14
|
||||
#define FR15 15
|
||||
#define FR16 16
|
||||
#define FR17 17
|
||||
#define FR18 18
|
||||
#define FR19 19
|
||||
#define FR20 20
|
||||
#define FR21 21
|
||||
#define FR22 22
|
||||
#define FR23 23
|
||||
#define FR24 24
|
||||
#define FR25 25
|
||||
#define FR26 26
|
||||
#define FR27 27
|
||||
#define FR28 28
|
||||
#define FR29 29
|
||||
#define FR30 30
|
||||
#define FR31 31
|
||||
|
||||
/* GPR register names (to be used as macro arguments) */
|
||||
#define R0 0
|
||||
#define R1 1
|
||||
#define R2 2
|
||||
#define R3 3
|
||||
#define R4 4
|
||||
#define R5 5
|
||||
#define R6 6
|
||||
#define R7 7
|
||||
#define R8 8
|
||||
#define R9 9
|
||||
#define R10 10
|
||||
#define R11 11
|
||||
#define R12 12
|
||||
#define R13 13
|
||||
#define R14 14
|
||||
#define R15 15
|
||||
#define R16 16
|
||||
#define R17 17
|
||||
#define R18 18
|
||||
#define R19 19
|
||||
#define R20 20
|
||||
#define R21 21
|
||||
#define R22 22
|
||||
#define R23 23
|
||||
#define R24 24
|
||||
#define R25 25
|
||||
#define R26 26
|
||||
#define R27 27
|
||||
#define R28 28
|
||||
#define R29 29
|
||||
#define R30 30
|
||||
#define R31 31
|
||||
|
||||
#ifndef __darwin__
|
||||
|
||||
/* GPR register names, rN -> N, frN -> N, vN -> N */
|
||||
mFORLOOP([i],0,31,[define(r[]i,[]i)])
|
||||
mFORLOOP([i],0,31,[define(fr[]i,[]i)])
|
||||
mFORLOOP([i],0,31,[define(v[]i,[]i)])
|
||||
|
||||
#endif /* __darwin__ */
|
||||
|
||||
|
||||
/************************************************************************/
|
||||
/* useful macros */
|
||||
/************************************************************************/
|
||||
|
||||
MACRO(ori_, [reg1, reg2, value], [
|
||||
.if (_value & 0xffff)
|
||||
ori _reg1, _reg2, (_value) & 0xffff
|
||||
.endif
|
||||
.if (_value & ~0xffff)
|
||||
oris _reg1, _reg2, (_value) >> 16
|
||||
.endif
|
||||
])
|
||||
#define r0 0
|
||||
#define r1 1
|
||||
#define r2 2
|
||||
#define r3 3
|
||||
#define r4 4
|
||||
#define r5 5
|
||||
#define r6 6
|
||||
#define r7 7
|
||||
#define r8 8
|
||||
#define r9 9
|
||||
#define r10 10
|
||||
#define r11 11
|
||||
#define r12 12
|
||||
#define r13 13
|
||||
#define r14 14
|
||||
#define r15 15
|
||||
#define r16 16
|
||||
#define r17 17
|
||||
#define r18 18
|
||||
#define r19 19
|
||||
#define r20 20
|
||||
#define r21 21
|
||||
#define r22 22
|
||||
#define r23 23
|
||||
#define r24 24
|
||||
#define r25 25
|
||||
#define r26 26
|
||||
#define r27 27
|
||||
#define r28 28
|
||||
#define r29 29
|
||||
#define r30 30
|
||||
#define r31 31
|
||||
|
||||
/************************************************************************/
|
||||
/* MISC */
|
||||
/************************************************************************/
|
||||
|
||||
#ifdef __linux__
|
||||
#ifndef __darwin__
|
||||
#define GLOBL( name ) .globl name ; name
|
||||
#define EXTERN( name ) name
|
||||
#else
|
||||
|
||||
Reference in New Issue
Block a user