Move AUX1 and AUX2 to correct locations, rename APC

git-svn-id: svn://coreboot.org/openbios/openbios-devel@185 f158a5a8-5612-0410-a976-696ce0be7e32
This commit is contained in:
Blue Swirl
2008-02-01 19:58:56 +00:00
parent 84659172f1
commit b56d6fd8a5
5 changed files with 34 additions and 20 deletions

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@@ -27,6 +27,7 @@ struct hwdef {
uint64_t iommu_base, slavio_base; uint64_t iommu_base, slavio_base;
uint64_t intctl_base, counter_base, nvram_base, ms_kb_base, serial_base; uint64_t intctl_base, counter_base, nvram_base, ms_kb_base, serial_base;
unsigned long fd_offset, counter_offset, intr_offset; unsigned long fd_offset, counter_offset, intr_offset;
unsigned long aux1_offset, aux2_offset;
uint64_t dma_base, esp_base, le_base; uint64_t dma_base, esp_base, le_base;
uint64_t tcx_base; uint64_t tcx_base;
int machine_id; int machine_id;
@@ -44,6 +45,8 @@ static const struct hwdef hwdefs[] = {
.fd_offset = 0x00400000, .fd_offset = 0x00400000,
.counter_offset = 0x00d00000, .counter_offset = 0x00d00000,
.intr_offset = 0x00e00000, .intr_offset = 0x00e00000,
.aux1_offset = 0x00900000,
.aux2_offset = 0x00910000,
.dma_base = 0x78400000, .dma_base = 0x78400000,
.esp_base = 0x78800000, .esp_base = 0x78800000,
.le_base = 0x78c00000, .le_base = 0x78c00000,
@@ -60,6 +63,8 @@ static const struct hwdef hwdefs[] = {
.fd_offset = 0x00700000, // 0xff1700000ULL, .fd_offset = 0x00700000, // 0xff1700000ULL,
.counter_offset = 0x00300000, // 0xff1300000ULL, .counter_offset = 0x00300000, // 0xff1300000ULL,
.intr_offset = 0x00400000, // 0xff1400000ULL, .intr_offset = 0x00400000, // 0xff1400000ULL,
.aux1_offset = 0x00800000, // 0xff1800000ULL,
.aux2_offset = 0x00a01000, // 0xff1a01000ULL,
.dma_base = 0xef0400000ULL, .dma_base = 0xef0400000ULL,
.esp_base = 0xef0800000ULL, .esp_base = 0xef0800000ULL,
.le_base = 0xef0c00000ULL, .le_base = 0xef0c00000ULL,
@@ -76,6 +81,8 @@ static const struct hwdef hwdefs[] = {
.fd_offset = -1, .fd_offset = -1,
.counter_offset = 0x00300000, // 0xff1300000ULL, .counter_offset = 0x00300000, // 0xff1300000ULL,
.intr_offset = 0x00400000, // 0xff1400000ULL, .intr_offset = 0x00400000, // 0xff1400000ULL,
.aux1_offset = 0x00800000, // 0xff1800000ULL,
.aux2_offset = 0x00a01000, // 0xff1a01000ULL, XXX should not exist
.dma_base = 0xef0081000ULL, .dma_base = 0xef0081000ULL,
.esp_base = 0xef0080000ULL, .esp_base = 0xef0080000ULL,
.le_base = 0xef0060000ULL, .le_base = 0xef0060000ULL,
@@ -109,7 +116,8 @@ arch_init( void )
ob_init_mmu(hwdef->iommu_base); ob_init_mmu(hwdef->iommu_base);
#ifdef CONFIG_DRIVER_OBIO #ifdef CONFIG_DRIVER_OBIO
ob_obio_init(hwdef->slavio_base, hwdef->fd_offset, ob_obio_init(hwdef->slavio_base, hwdef->fd_offset,
hwdef->counter_offset, hwdef->intr_offset); hwdef->counter_offset, hwdef->intr_offset,
hwdef->aux1_offset, hwdef->aux2_offset);
nvram_init(); nvram_init();
#endif #endif
#ifdef CONFIG_DRIVER_SBUS #ifdef CONFIG_DRIVER_SBUS

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@@ -1048,12 +1048,13 @@ sparc32_reset_all(void)
*reset_reg = 1; *reset_reg = 1;
} }
// AUX 2 (Software Powerdown Control) and reset
static void static void
ob_power_init(uint64_t base, uint64_t offset, int intr) ob_aux2_reset_init(uint64_t base, uint64_t offset, int intr)
{ {
ob_new_obio_device("power", NULL); ob_new_obio_device("power", NULL);
power_reg = ob_reg(base, offset, POWER_REGS, 1); power_reg = ob_reg(base, offset, AUXIO2_REGS, 1);
// Not in device tree // Not in device tree
reset_reg = map_io(base + (uint64_t)SLAVIO_RESET, RESET_REGS); reset_reg = map_io(base + (uint64_t)SLAVIO_RESET, RESET_REGS);
@@ -1284,7 +1285,8 @@ NODE_METHODS(ob_obio) = {
int int
ob_obio_init(uint64_t slavio_base, unsigned long fd_offset, ob_obio_init(uint64_t slavio_base, unsigned long fd_offset,
unsigned long counter_offset, unsigned long intr_offset) unsigned long counter_offset, unsigned long intr_offset,
unsigned long aux1_offset, unsigned long aux2_offset)
{ {
// All devices were integrated to NCR89C105, see // All devices were integrated to NCR89C105, see
@@ -1312,9 +1314,10 @@ ob_obio_init(uint64_t slavio_base, unsigned long fd_offset,
ob_sconfig_init(slavio_base, SLAVIO_SCONFIG); ob_sconfig_init(slavio_base, SLAVIO_SCONFIG);
ob_auxio_init(slavio_base, SLAVIO_AUXIO); ob_auxio_init(slavio_base, aux1_offset);
ob_power_init(slavio_base, SLAVIO_POWER, POWER_INTR); if (aux2_offset != (unsigned long) -1)
ob_aux2_reset_init(slavio_base, aux2_offset, AUXIO2_INTR);
ob_counter_init(slavio_base, counter_offset); ob_counter_init(slavio_base, counter_offset);

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@@ -16,12 +16,10 @@
#define SLAVIO_SCONFIG 0x00800000ULL #define SLAVIO_SCONFIG 0x00800000ULL
#define SCONFIG_REGS 1 #define SCONFIG_REGS 1
#define SLAVIO_AUXIO 0x00900000ULL
#define AUXIO_REGS 1 #define AUXIO_REGS 1
#define SLAVIO_POWER 0x00910000ULL #define AUXIO2_REGS 1
#define POWER_REGS 1 #define AUXIO2_INTR 0x22
#define POWER_INTR 0x22
#define SLAVIO_COUNTER 0x00d00000ULL #define SLAVIO_COUNTER 0x00d00000ULL
#define COUNTER_REGS 0x10 #define COUNTER_REGS 0x10

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@@ -20,8 +20,8 @@
#define SBUS_REGS 0x28 #define SBUS_REGS 0x28
#define SBUS_SLOTS 16 #define SBUS_SLOTS 16
#define POWER_REGS 0x10 #define APC_REGS 0x10
#define POWER_OFFSET 0x0a000000ULL #define APC_OFFSET 0x0a000000ULL
#define CS4231_REGS 0x40 #define CS4231_REGS 0x40
#define CS4231_OFFSET 0x0c000000ULL #define CS4231_OFFSET 0x0c000000ULL
#define MACIO_ESPDMA 0x00400000ULL /* ESP DMA controller */ #define MACIO_ESPDMA 0x00400000ULL /* ESP DMA controller */
@@ -281,7 +281,7 @@ ob_tcx_init(unsigned int slot, unsigned long base)
} }
static void static void
ob_power_init(unsigned int slot, unsigned long base) ob_apc_init(unsigned int slot, unsigned long base)
{ {
push_str("/iommu/sbus"); push_str("/iommu/sbus");
fword("find-device"); fword("find-device");
@@ -295,7 +295,7 @@ ob_power_init(unsigned int slot, unsigned long base)
PUSH(base); PUSH(base);
fword("encode-int"); fword("encode-int");
fword("encode+"); fword("encode+");
PUSH(POWER_REGS); PUSH(APC_REGS);
fword("encode-int"); fword("encode-int");
fword("encode+"); fword("encode+");
push_str("reg"); push_str("reg");
@@ -366,9 +366,6 @@ ob_macio_init(unsigned int slot, uint64_t base, unsigned long offset)
// Parallel port // Parallel port
//ob_bpp_init(base); //ob_bpp_init(base);
// Power management
ob_power_init(slot, POWER_OFFSET);
} }
static void static void
@@ -379,10 +376,13 @@ sbus_probe_slot_ss5(unsigned int slot, uint64_t base)
case 3: // SUNW,tcx case 3: // SUNW,tcx
ob_tcx_init(slot, base); ob_tcx_init(slot, base);
break; break;
case 4: // SUNW,CS4231 case 4:
// SUNW,CS4231
ob_cs4231_init(slot, base); ob_cs4231_init(slot, base);
// Power management (APC)
ob_apc_init(slot, APC_OFFSET);
break; break;
case 5: // MACIO: le, esp, bpp, power-management case 5: // MACIO: le, esp, bpp
ob_macio_init(slot, base, 0x08000000); ob_macio_init(slot, base, 0x08000000);
break; break;
default: default:
@@ -400,6 +400,8 @@ sbus_probe_slot_ss10(unsigned int slot, uint64_t base)
break; break;
case 0xf: // le, esp, bpp, power-management case 0xf: // le, esp, bpp, power-management
ob_macio_init(slot, base, 0); ob_macio_init(slot, base, 0);
// Power management (APC) XXX should not exist
ob_apc_init(slot, APC_OFFSET);
break; break;
default: default:
break; break;
@@ -420,6 +422,8 @@ sbus_probe_slot_ss600mp(unsigned int slot, uint64_t base)
#endif #endif
// NCR 92C990, Am7990, Lance. See http://www.amd.com // NCR 92C990, Am7990, Lance. See http://www.amd.com
ob_le_init(slot, base, 0x00060000, SS600MP_LEBUFFER); ob_le_init(slot, base, 0x00060000, SS600MP_LEBUFFER);
// Power management (APC) XXX should not exist
ob_apc_init(slot, APC_OFFSET);
break; break;
default: default:
break; break;

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@@ -26,6 +26,7 @@ int ob_esp_init(unsigned int slot, uint64_t base, unsigned long espoffset,
#endif #endif
#ifdef CONFIG_DRIVER_OBIO #ifdef CONFIG_DRIVER_OBIO
int ob_obio_init(uint64_t slavio_base, unsigned long fd_offset, int ob_obio_init(uint64_t slavio_base, unsigned long fd_offset,
unsigned long counter_offset, unsigned long intr_offset); unsigned long counter_offset, unsigned long intr_offset,
unsigned long aux1_offset, unsigned long aux2_offset);
#endif #endif