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fix messed up commit.

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git-svn-id: svn://coreboot.org/openbios/openbios-devel@14 f158a5a8-5612-0410-a976-696ce0be7e32
This commit is contained in:
Stefan Reinauer
2006-05-08 10:48:38 +00:00
parent 1ab6b463ad
commit d421756207
6 changed files with 0 additions and 1244 deletions
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269
drivers/esp.h
View File

@@ -267,272 +267,3 @@ enum esp_rev {
#define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
#endif /* !(_SPARC_ESP_H) */
/* $Id: esp.h,v 1.28 2000/03/30 01:33:17 davem Exp $
* esp.h: Defines and structures for the Sparc ESP (Enhanced SCSI
* Processor) driver under Linux.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC_ESP_H
#define _SPARC_ESP_H
/* For dvma controller register definitions. */
#include <asm/dma.h>
/* The ESP SCSI controllers have their register sets in three
* "classes":
*
* 1) Registers which are both read and write.
* 2) Registers which are read only.
* 3) Registers which are write only.
*
* Yet, they all live within the same IO space.
*/
/* All the ESP registers are one byte each and are accessed longwords
* apart with a big-endian ordering to the bytes.
*/
/* Access Description Offset */
#define ESP_TCLOW 0x00UL /* rw Low bits of the transfer count 0x00 */
#define ESP_TCMED 0x04UL /* rw Mid bits of the transfer count 0x04 */
#define ESP_FDATA 0x08UL /* rw FIFO data bits 0x08 */
#define ESP_CMD 0x0cUL /* rw SCSI command bits 0x0c */
#define ESP_STATUS 0x10UL /* ro ESP status register 0x10 */
#define ESP_BUSID ESP_STATUS /* wo Bus ID for select/reselect 0x10 */
#define ESP_INTRPT 0x14UL /* ro Kind of interrupt 0x14 */
#define ESP_TIMEO ESP_INTRPT /* wo Timeout value for select/resel 0x14 */
#define ESP_SSTEP 0x18UL /* ro Sequence step register 0x18 */
#define ESP_STP ESP_SSTEP /* wo Transfer period per sync 0x18 */
#define ESP_FFLAGS 0x1cUL /* ro Bits of current FIFO info 0x1c */
#define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */
#define ESP_CFG1 0x20UL /* rw First configuration register 0x20 */
#define ESP_CFACT 0x24UL /* wo Clock conversion factor 0x24 */
#define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */
#define ESP_CTEST 0x28UL /* wo Chip test register 0x28 */
#define ESP_CFG2 0x2cUL /* rw Second configuration register 0x2c */
#define ESP_CFG3 0x30UL /* rw Third configuration register 0x30 */
#define ESP_TCHI 0x38UL /* rw High bits of transfer count 0x38 */
#define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */
#define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */
#define ESP_FGRND 0x3cUL /* rw Data base for fifo 0x3c */
#define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */
#define ESP_REG_SIZE 0x40UL
/* Various revisions of the ESP board. */
enum esp_rev {
esp100 = 0x00, /* NCR53C90 - very broken */
esp100a = 0x01, /* NCR53C90A */
esp236 = 0x02,
fas236 = 0x03,
fas100a = 0x04,
fast = 0x05,
fashme = 0x06,
espunknown = 0x07
};
/* Bitfield meanings for the above registers. */
/* ESP config reg 1, read-write, found on all ESP chips */
#define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
#define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
#define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */
#define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */
#define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */
#define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */
/* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
#define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */
#define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */
#define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */
#define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tmode only) */
#define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */
#define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */
#define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
#define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */
#define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,esp216) */
#define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (esp236) */
#define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */
#define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */
#define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */
/* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
#define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */
#define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
#define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */
#define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */
#define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */
#define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */
#define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */
#define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */
#define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */
#define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */
#define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */
#define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */
#define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */
#define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */
#define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */
#define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */
/* ESP command register read-write */
/* Group 1 commands: These may be sent at any point in time to the ESP
* chip. None of them can generate interrupts 'cept
* the "SCSI bus reset" command if you have not disabled
* SCSI reset interrupts in the config1 ESP register.
*/
#define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */
#define ESP_CMD_FLUSH 0x01 /* FIFO Flush */
#define ESP_CMD_RC 0x02 /* Chip reset */
#define ESP_CMD_RS 0x03 /* SCSI bus reset */
/* Group 2 commands: ESP must be an initiator and connected to a target
* for these commands to work.
*/
#define ESP_CMD_TI 0x10 /* Transfer Information */
#define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */
#define ESP_CMD_MOK 0x12 /* Message okie-dokie */
#define ESP_CMD_TPAD 0x18 /* Transfer Pad */
#define ESP_CMD_SATN 0x1a /* Set ATN */
#define ESP_CMD_RATN 0x1b /* De-assert ATN */
/* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected
* to a target as the initiator for these commands to work.
*/
#define ESP_CMD_SMSG 0x20 /* Send message */
#define ESP_CMD_SSTAT 0x21 /* Send status */
#define ESP_CMD_SDATA 0x22 /* Send data */
#define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */
#define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */
#define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */
#define ESP_CMD_DCNCT 0x27 /* Disconnect */
#define ESP_CMD_RMSG 0x28 /* Receive Message */
#define ESP_CMD_RCMD 0x29 /* Receive Command */
#define ESP_CMD_RDATA 0x2a /* Receive Data */
#define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */
/* Group 4 commands: The ESP must be in the disconnected state and must
* not be connected to any targets as initiator for
* these commands to work.
*/
#define ESP_CMD_RSEL 0x40 /* Reselect */
#define ESP_CMD_SEL 0x41 /* Select w/o ATN */
#define ESP_CMD_SELA 0x42 /* Select w/ATN */
#define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */
#define ESP_CMD_ESEL 0x44 /* Enable selection */
#define ESP_CMD_DSEL 0x45 /* Disable selections */
#define ESP_CMD_SA3 0x46 /* Select w/ATN3 */
#define ESP_CMD_RSEL3 0x47 /* Reselect3 */
/* This bit enables the ESP's DMA on the SBus */
#define ESP_CMD_DMA 0x80 /* Do DMA? */
/* ESP status register read-only */
#define ESP_STAT_PIO 0x01 /* IO phase bit */
#define ESP_STAT_PCD 0x02 /* CD phase bit */
#define ESP_STAT_PMSG 0x04 /* MSG phase bit */
#define ESP_STAT_PMASK 0x07 /* Mask of phase bits */
#define ESP_STAT_TDONE 0x08 /* Transfer Completed */
#define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */
#define ESP_STAT_PERR 0x20 /* Parity error */
#define ESP_STAT_SPAM 0x40 /* Real bad error */
/* This indicates the 'interrupt pending' condition on esp236, it is a reserved
* bit on other revs of the ESP.
*/
#define ESP_STAT_INTR 0x80 /* Interrupt */
/* HME only: status 2 register */
#define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */
#define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */
#define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */
#define ESP_STAT2_CREGA 0x08 /* The command reg is active now */
#define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */
#define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */
#define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */
#define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */
/* The status register can be masked with ESP_STAT_PMASK and compared
* with the following values to determine the current phase the ESP
* (at least thinks it) is in. For our purposes we also add our own
* software 'done' bit for our phase management engine.
*/
#define ESP_DOP (0) /* Data Out */
#define ESP_DIP (ESP_STAT_PIO) /* Data In */
#define ESP_CMDP (ESP_STAT_PCD) /* Command */
#define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */
#define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */
#define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
/* ESP interrupt register read-only */
#define ESP_INTR_S 0x01 /* Select w/o ATN */
#define ESP_INTR_SATN 0x02 /* Select w/ATN */
#define ESP_INTR_RSEL 0x04 /* Reselected */
#define ESP_INTR_FDONE 0x08 /* Function done */
#define ESP_INTR_BSERV 0x10 /* Bus service */
#define ESP_INTR_DC 0x20 /* Disconnect */
#define ESP_INTR_IC 0x40 /* Illegal command given */
#define ESP_INTR_SR 0x80 /* SCSI bus reset detected */
/* Interrupt status macros */
#define ESP_SRESET_IRQ(esp) ((esp)->intreg & (ESP_INTR_SR))
#define ESP_ILLCMD_IRQ(esp) ((esp)->intreg & (ESP_INTR_IC))
#define ESP_SELECT_WITH_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_SATN))
#define ESP_SELECT_WITHOUT_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_S))
#define ESP_SELECTION_IRQ(esp) ((ESP_SELECT_WITH_ATN_IRQ(esp)) || \
(ESP_SELECT_WITHOUT_ATN_IRQ(esp)))
#define ESP_RESELECTION_IRQ(esp) ((esp)->intreg & (ESP_INTR_RSEL))
/* ESP sequence step register read-only */
#define ESP_STEP_VBITS 0x07 /* Valid bits */
#define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */
#define ESP_STEP_SID 0x01 /* One msg byte sent */
#define ESP_STEP_NCMD 0x02 /* Was not in command phase */
#define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
* bytes to be lost
*/
#define ESP_STEP_FINI4 0x04 /* Command was sent ok */
/* Ho hum, some ESP's set the step register to this as well... */
#define ESP_STEP_FINI5 0x05
#define ESP_STEP_FINI6 0x06
#define ESP_STEP_FINI7 0x07
/* ESP chip-test register read-write */
#define ESP_TEST_TARG 0x01 /* Target test mode */
#define ESP_TEST_INI 0x02 /* Initiator test mode */
#define ESP_TEST_TS 0x04 /* Tristate test mode */
/* ESP unique ID register read-only, found on fas236+fas100a only */
#define ESP_UID_F100A 0x00 /* ESP FAS100A */
#define ESP_UID_F236 0x02 /* ESP FAS236 */
#define ESP_UID_REV 0x07 /* ESP revision */
#define ESP_UID_FAM 0xf8 /* ESP family */
/* ESP fifo flags register read-only */
/* Note that the following implies a 16 byte FIFO on the ESP. */
#define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */
#define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */
#define ESP_FF_SSTEP 0xe0 /* Sequence step */
/* ESP clock conversion factor register write-only */
#define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
#define ESP_CCF_NEVER 0x01 /* Set it to this and die */
#define ESP_CCF_F2 0x02 /* 10MHz */
#define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
#define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
#define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
#define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
#define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
/* HME only... */
#define ESP_BUSID_RESELID 0x10
#define ESP_BUSID_CTR32BIT 0x40
#define ESP_BUS_TIMEOUT 275 /* In milli-seconds */
#define ESP_TIMEO_CONST 8192
#define ESP_NEG_DEFP(mhz, cfact) \
((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
#define ESP_MHZ_TO_CYCLE(mhertz) ((1000000000) / ((mhertz) / 1000))
#define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
#endif /* !(_SPARC_ESP_H) */

372
drivers/iommu.c
View File

@@ -350,375 +350,3 @@ iommu_init(struct iommu *t)
mem_init(&t->bmap, (char*)t->plow, (char *)0xfffff000);
}
/**
** Proll (PROM replacement)
** iommu.c: Functions for DVMA management.
** Copyright 1999 Pete Zaitcev
** This code is licensed under GNU General Public License.
**/
#include "openbios/config.h"
#include "openbios/bindings.h"
#include "openbios/kernel.h"
#include "libc/byteorder.h"
#include "libc/vsprintf.h"
#include "libc/string.h"
#include "openbios/drivers.h"
#include "asm/asi.h"
#include "asm/crs.h"
#include "pgtsrmmu.h"
#include "iommu.h"
#define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */
#define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
#define MKIOPTE(phys) (((((phys)>>4) & IOPTE_PAGE) | IOPERM) & ~IOPTE_WAZ)
#define LOWMEMSZ 32 * 1024 * 1024
/*
* Allocatable memory chunk.
*/
struct mem {
char *start, *uplim;
char *curp;
};
struct mem cmem; /* Current memory, virtual */
struct mem cio; /* Current I/O space */
unsigned long *context_table;
unsigned long *l1;
/*
* IOMMU parameters
*/
struct iommu {
struct iommu_regs *regs;
unsigned int *page_table;
unsigned long plow; /* Base bus address */
unsigned long vasize; /* Size of VA region that we manage */
struct mem bmap;
};
struct iommu ciommu;
#define NCTX_SWIFT 0x100
unsigned int va_shift; // Set in entry.S
extern char _start, _data, _end, _vmem, _evmem, _iomem; // Defined in ldscript
static unsigned long
va2pa(unsigned long va)
{
if ((va >= (unsigned long)&_data) &&
(va < (unsigned long)&_end))
return va - va_shift;
else
return va;
}
static unsigned long
pa2va(unsigned long pa)
{
if ((pa + va_shift >= (unsigned long)&_data) &&
(pa + va_shift< (unsigned long)&_end))
return pa + va_shift;
else
return pa;
}
static void iommu_init(struct iommu *t);
static void
iommu_invalidate(struct iommu_regs *regs) {
regs->tlbflush = 0;
}
/*
* Allocate memory. This is reusable.
*/
void
mem_init(struct mem *t, char *begin, char *limit)
{
t->start = begin;
t->uplim = limit;
t->curp = begin;
}
void
mem_fini(struct mem *t)
{
t->curp = 0;
}
void *
mem_alloc(struct mem *t, int size, int align)
{
char *p;
p = (char *)((((unsigned int)t->curp) + (align-1)) & ~(align-1));
if (p >= t->uplim || p + size > t->uplim)
return 0;
t->curp = p + size;
return p;
}
void *
mem_zalloc(struct mem *t, int size, int align)
{
char *p;
if ((p = mem_alloc(t, size, align)) != 0)
memset(p, 0, size);
return p;
}
/*
* Create a memory mapping from va to epa in page table pgd.
* highbase is used for v2p translation.
*/
int
map_page(unsigned long *pgd, unsigned long va,
unsigned long epa, int type)
{
uint32_t pte;
void *p;
unsigned long pa;
pte = pgd[(va >> SRMMU_PGDIR_SHIFT) & (SRMMU_PTRS_PER_PGD - 1)];
if ((pte & SRMMU_ET_MASK) == SRMMU_ET_INVALID) {
p = mem_zalloc(&cmem, SRMMU_PTRS_PER_PMD * sizeof(int),
SRMMU_PTRS_PER_PMD * sizeof(int));
if (p == 0)
goto drop;
pte = SRMMU_ET_PTD | ((va2pa((unsigned long)p)) >> 4);
pgd[(va >> SRMMU_PGDIR_SHIFT) & (SRMMU_PTRS_PER_PGD - 1)] = pte;
/* barrier() */
}
pa = (pte & 0xFFFFFFF0) << 4;
pa += ((va >> SRMMU_PMD_SHIFT) & (SRMMU_PTRS_PER_PMD - 1)) << 2;
pte = *(uint32_t *)pa2va(pa);
if ((pte & SRMMU_ET_MASK) == SRMMU_ET_INVALID) {
p = mem_zalloc(&cmem, SRMMU_PTRS_PER_PTE * sizeof(void *),
SRMMU_PTRS_PER_PTE * sizeof(void *));
if (p == 0)
goto drop;
pte = SRMMU_ET_PTD | ((va2pa((unsigned int)p)) >> 4);
*(uint32_t *)pa2va(pa) = pte;
}
pa = (pte & 0xFFFFFFF0) << 4;
pa += ((va >> PAGE_SHIFT) & (SRMMU_PTRS_PER_PTE - 1)) << 2;
pte = SRMMU_ET_PTE | ((epa & PAGE_MASK) >> 4);
if (type) { /* I/O */
pte |= SRMMU_REF;
/* SRMMU cannot make Supervisor-only, but not exectutable */
pte |= SRMMU_PRIV;
} else { /* memory */
pte |= SRMMU_REF | SRMMU_CACHE;
pte |= SRMMU_PRIV; /* Supervisor only access */
}
*(uint32_t *)pa2va(pa) = pte;
//printk("map_page: va 0x%lx pa 0x%lx pte 0x%x\n", va, epa, pte);
return 0;
drop:
return -1;
}
/*
* Create an I/O mapping to pa[size].
* Returns va of the mapping or 0 if unsuccessful.
*/
void *
map_io(unsigned pa, int size)
{
void *va;
unsigned int npages;
unsigned int off;
unsigned int mva;
off = pa & (PAGE_SIZE - 1);
npages = (off + size + (PAGE_SIZE - 1)) / PAGE_SIZE;
pa &= ~(PAGE_SIZE - 1);
va = mem_alloc(&cio, npages * PAGE_SIZE, PAGE_SIZE);
if (va == 0)
return va;
mva = (unsigned int) va;
printk("map_io: va 0x%p pa 0x%x off 0x%x npages %d\n", va, pa, off, npages); /* P3 */
while (npages-- != 0) {
map_page(l1, mva, pa, 1);
mva += PAGE_SIZE;
pa += PAGE_SIZE;
}
return (void *)((unsigned int)va + off);
}
/*
* Switch page tables.
*/
void
init_mmu_swift()
{
unsigned int addr, i;
unsigned long pa, va;
mem_init(&cmem, (char *) &_vmem, (char *)&_evmem);
mem_init(&cio, (char *)&_end, (char *)&_iomem);
context_table = mem_zalloc(&cmem, NCTX_SWIFT * sizeof(int), NCTX_SWIFT * sizeof(int));
l1 = mem_zalloc(&cmem, 256 * sizeof(int), 256 * sizeof(int));
context_table[0] = (((unsigned long)va2pa((unsigned long)l1)) >> 4) | SRMMU_ET_PTD;
for (i = 1; i < NCTX_SWIFT; i++) {
context_table[i] = SRMMU_ET_INVALID;
}
for (i = 0; i < 256; i += 4) {
l1[i] = SRMMU_ET_INVALID;
}
// 1:1 mapping for ROM
pa = va = (unsigned long)&_start;
for (; va < (unsigned long)&_data; va += PAGE_SIZE, pa += PAGE_SIZE) {
map_page(l1, va, pa, 0);
}
// data & bss mapped to end of RAM
va = (unsigned long)&_data;
for (; va < (unsigned long)&_end; va += PAGE_SIZE) {
pa = va2pa(va);
map_page(l1, va, pa, 0);
}
// 1:1 mapping for RAM
pa = va = 0;
for (; va < LOWMEMSZ; va += PAGE_SIZE, pa += PAGE_SIZE) {
map_page(l1, va, pa, 0);
}
/*
* Flush cache
*/
for (addr = 0; addr < 0x2000; addr += 0x10) {
__asm__ __volatile__ ("sta %%g0, [%0] %1\n\t" : :
"r" (addr), "i" (ASI_M_DATAC_TAG));
__asm__ __volatile__ ("sta %%g0, [%0] %1\n\t" : :
"r" (addr<<1), "i" (ASI_M_TXTC_TAG));
}
srmmu_set_context(0);
srmmu_set_ctable_ptr(va2pa((unsigned long)context_table));
srmmu_flush_whole_tlb();
iommu_init(&ciommu);
}
/*
* XXX This is a problematic interface. We alloc _memory_ which is uncached.
* So if we ever reuse allocations somebody is going to get uncached pages.
* Returned address is always aligned by page.
* BTW, we were not going to give away anonymous storage, were we not?
*/
void *
dvma_alloc(int size, unsigned int *pphys)
{
void *va;
unsigned int pa, ba;
unsigned int npages;
unsigned int mva, mpa;
unsigned int i;
unsigned int *iopte;
struct iommu *t = &ciommu;
npages = (size + (PAGE_SIZE-1)) / PAGE_SIZE;
va = mem_alloc(&cmem, npages * PAGE_SIZE, PAGE_SIZE);
if (va == 0)
return 0;
ba = (unsigned int)mem_alloc(&t->bmap, npages * PAGE_SIZE, PAGE_SIZE);
if (ba == 0)
return 0;
pa = (unsigned int)va2pa(va);
/*
* Change page attributes in MMU to uncached.
*/
mva = (unsigned int) va;
mpa = (unsigned int) pa;
for (i = 0; i < npages; i++) {
map_page(l1, mva, mpa, 1);
mva += PAGE_SIZE;
mpa += PAGE_SIZE;
}
/*
* Map into IOMMU page table.
*/
mpa = (unsigned int) pa;
iopte = &t->page_table[(ba - t->plow) / PAGE_SIZE];
for (i = 0; i < npages; i++) {
*iopte++ = MKIOPTE(mpa);
mpa += PAGE_SIZE;
}
*pphys = ba;
return va;
}
/*
* Initialize IOMMU
* This looks like initialization of CPU MMU but
* the routine is higher in food chain.
*/
static void
iommu_init(struct iommu *t)
{
unsigned int *ptab;
int ptsize;
struct iommu_regs *regs =NULL;
unsigned int impl, vers;
unsigned int tmp;
if ((regs = map_io(PHYS_JJ_IOMMU, sizeof(struct iommu_regs))) == 0) {
printk("Cannot map IOMMU\n");
for (;;) { }
}
t->regs = regs;
impl = (regs->control & IOMMU_CTRL_IMPL) >> 28;
vers = (regs->control & IOMMU_CTRL_VERS) >> 24;
tmp = regs->control;
tmp &= ~(IOMMU_CTRL_RNGE);
tmp |= (IOMMU_RNGE_32MB | IOMMU_CTRL_ENAB);
t->plow = 0xfe000000; /* End - 32 MB */
t->vasize = 0x2000000; /* 32 MB */
regs->control = tmp;
iommu_invalidate(regs);
/* Allocate IOMMU page table */
/* Thremendous alignment causes great waste... */
ptsize = (t->vasize/PAGE_SIZE) * sizeof(int);
if ((ptab = mem_zalloc(&cmem, ptsize, ptsize)) == 0) {
printk("Cannot allocate IOMMU table [0x%x]\n", ptsize);
for (;;) { }
}
t->page_table = ptab;
/* flush_cache_all(); */
/** flush_tlb_all(); **/
regs->base = ((unsigned int)va2pa((unsigned long)ptab)) >> 4;
iommu_invalidate(regs);
printk("IOMMU: impl %d vers %d page table at 0x%p of size %d bytes\n",
impl, vers, t->page_table, ptsize);
mem_init(&t->bmap, (char*)t->plow, (char *)0xfffff000);
}

97
drivers/iommu.h
View File

@@ -95,100 +95,3 @@ struct iommu_regs {
#define IOPTE_WRITE 0x00000004 /* Writeable */
#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ 0x00000001 /* Write as zeros */
/* iommu.h: Definitions for the sun4m IOMMU.
*
* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
* Adapted for Proll by Pete Zaitcev in 1999 (== made worse than original).
*/
/* #include <asm/page.h> */
/* The iommu handles all virtual to physical address translations
* that occur between the SBUS and physical memory. Access by
* the cpu to IO registers and similar go over the mbus so are
* translated by the on chip SRMMU. The iommu and the srmmu do
* not need to have the same translations at all, in fact most
* of the time the translations they handle are a disjunct set.
* Basically the iommu handles all dvma sbus activity.
*/
/* The IOMMU registers occupy three pages in IO space. */
struct iommu_regs {
/* First page */
volatile unsigned long control; /* IOMMU control */
volatile unsigned long base; /* Physical base of iopte page table */
volatile unsigned long _unused1[3];
volatile unsigned long tlbflush; /* write only */
volatile unsigned long pageflush; /* write only */
volatile unsigned long _unused2[1017];
/* Second page */
volatile unsigned long afsr; /* Async-fault status register */
volatile unsigned long afar; /* Async-fault physical address */
volatile unsigned long _unused3[2];
volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
volatile unsigned long sbuscfg1;
volatile unsigned long sbuscfg2;
volatile unsigned long sbuscfg3;
volatile unsigned long mfsr; /* Memory-fault status register */
volatile unsigned long mfar; /* Memory-fault physical address */
volatile unsigned long _unused4[1014];
/* Third page */
volatile unsigned long mid; /* IOMMU module-id */
};
#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
produced by this device as pure
physical. */
#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
on the even word of the access, low bit
indicated odd word caused the parity error */
#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
/* The format of an iopte in the page tables */
#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
#define IOPTE_WRITE 0x00000004 /* Writeable */
#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ 0x00000001 /* Write as zeros */

230
drivers/pgtsrmmu.h
View File

@@ -184,236 +184,6 @@ extern __inline__ void srmmu_flush_tlb_region(unsigned long addr)
}
extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
{
addr &= SRMMU_PMD_MASK;
__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
"r" (addr | 0x100), /* Flush TLB segment.. */
"i" (ASI_M_FLUSH_PROBE) : "memory");
}
extern __inline__ void srmmu_flush_tlb_page(unsigned long page)
{
page &= PAGE_MASK;
__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
"r" (page), /* Flush TLB page.. */
"i" (ASI_M_FLUSH_PROBE) : "memory");
}
extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
{
unsigned long retval;
vaddr &= PAGE_MASK;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
return retval;
}
extern __inline__ int
srmmu_get_pte (unsigned long addr)
{
register unsigned long entry;
__asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
"=r" (entry):
"r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
return entry;
}
#endif /* !(__ASSEMBLY__) */
#endif /* !(_SPARC_PGTSRMMU_H) */
/*
* Taken from kernel for decoupling from <asm/page.h>. --zaitcev
*
* $Id: pgtsrmmu.h,v 1.2 1999/04/19 01:04:31 zaitcev Exp $
* pgtsrmmu.h: SRMMU page table defines and code.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _PGTSRMMU_H
#define _PGTSRMMU_H
/* Replacement for <asm/page.h> */
#define PAGE_SHIFT 12
#define PAGE_SIZE (1 << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
/* */
/* PMD_SHIFT determines the size of the area a second-level page table can map */
#define SRMMU_PMD_SHIFT 18
#define SRMMU_PMD_SIZE (1UL << SRMMU_PMD_SHIFT)
#define SRMMU_PMD_MASK (~(SRMMU_PMD_SIZE-1))
#define SRMMU_PMD_ALIGN(addr) (((addr)+SRMMU_PMD_SIZE-1)&SRMMU_PMD_MASK)
/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define SRMMU_PGDIR_SHIFT 24
#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
#define SRMMU_PTRS_PER_PTE 64
#define SRMMU_PTRS_PER_PMD 64
#define SRMMU_PTRS_PER_PGD 256
#define SRMMU_PTE_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */
#define SRMMU_PMD_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */
#define SRMMU_PGD_TABLE_SIZE 0x400 /* 256 entries, 4 bytes a piece */
#define SRMMU_VMALLOC_START (0xfe300000)
#define SRMMU_VMALLOC_END ~0x0UL
/* Definition of the values in the ET field of PTD's and PTE's */
#define SRMMU_ET_MASK 0x3
#define SRMMU_ET_INVALID 0x0
#define SRMMU_ET_PTD 0x1
#define SRMMU_ET_PTE 0x2
#define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
/* Physical page extraction from PTP's and PTE's. */
#define SRMMU_CTX_PMASK 0xfffffff0
#define SRMMU_PTD_PMASK 0xfffffff0
#define SRMMU_PTE_PMASK 0xffffff00
/* The pte non-page bits. Some notes:
* 1) cache, dirty, valid, and ref are frobbable
* for both supervisor and user pages.
* 2) exec and write will only give the desired effect
* on user pages
* 3) use priv and priv_readonly for changing the
* characteristics of supervisor ptes
*/
#define SRMMU_CACHE 0x80
#define SRMMU_DIRTY 0x40
#define SRMMU_REF 0x20
#define SRMMU_EXEC 0x08
#define SRMMU_WRITE 0x04
#define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
#define SRMMU_PRIV 0x1c
#define SRMMU_PRIV_RDONLY 0x18
#define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
/* SRMMU Register addresses in ASI 0x4. These are valid for all
* current SRMMU implementations that exist.
*/
#define SRMMU_CTRL_REG 0x00000000
#define SRMMU_CTXTBL_PTR 0x00000100
#define SRMMU_CTX_REG 0x00000200
#define SRMMU_FAULT_STATUS 0x00000300
#define SRMMU_FAULT_ADDR 0x00000400
#ifndef __ASSEMBLY__
/* Accessing the MMU control register. */
extern __inline__ unsigned int srmmu_get_mmureg(void)
{
unsigned int retval;
__asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
"=r" (retval) :
"i" (ASI_M_MMUREGS));
return retval;
}
extern __inline__ void srmmu_set_mmureg(unsigned long regval)
{
__asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
"r" (regval), "i" (ASI_M_MMUREGS) : "memory");
}
extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
{
paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
"r" (paddr), "r" (SRMMU_CTXTBL_PTR),
"i" (ASI_M_MMUREGS) :
"memory");
}
extern __inline__ unsigned long srmmu_get_ctable_ptr(void)
{
unsigned int retval;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (SRMMU_CTXTBL_PTR),
"i" (ASI_M_MMUREGS));
return (retval & SRMMU_CTX_PMASK) << 4;
}
extern __inline__ void srmmu_set_context(int context)
{
__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
"r" (context), "r" (SRMMU_CTX_REG),
"i" (ASI_M_MMUREGS) : "memory");
}
extern __inline__ int srmmu_get_context(void)
{
register int retval;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (SRMMU_CTX_REG),
"i" (ASI_M_MMUREGS));
return retval;
}
extern __inline__ unsigned int srmmu_get_fstatus(void)
{
unsigned int retval;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
return retval;
}
extern __inline__ unsigned int srmmu_get_faddr(void)
{
unsigned int retval;
__asm__ __volatile__("lda [%1] %2, %0\n\t" :
"=r" (retval) :
"r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
return retval;
}
/* This is guaranteed on all SRMMU's. */
extern __inline__ void srmmu_flush_whole_tlb(void)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
"r" (0x400), /* Flush entire TLB!! */
"i" (ASI_M_FLUSH_PROBE) : "memory");
}
/* These flush types are not available on all chips... */
extern __inline__ void srmmu_flush_tlb_ctx(void)
{
__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
"r" (0x300), /* Flush TLB ctx.. */
"i" (ASI_M_FLUSH_PROBE) : "memory");
}
extern __inline__ void srmmu_flush_tlb_region(unsigned long addr)
{
addr &= SRMMU_PGDIR_MASK;
__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
"r" (addr | 0x200), /* Flush TLB region.. */
"i" (ASI_M_FLUSH_PROBE) : "memory");
}
extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
{
addr &= SRMMU_PMD_MASK;

262
drivers/scsi.h
View File

@@ -260,265 +260,3 @@ struct ccs_modesel_head
*/
#endif
#ifndef _LINUX_SCSI_H
#define _LINUX_SCSI_H
/*
* This header file contains public constants and structures used by
* the scsi code for linux.
*/
/*
$Header: /usr/src/linux/include/linux/RCS/scsi.h,v 1.3 1993/09/24 12:20:33 drew Exp $
For documentation on the OPCODES, MESSAGES, and SENSE values,
please consult the SCSI standard.
*/
/*
* SCSI opcodes
*/
#define TEST_UNIT_READY 0x00
#define REZERO_UNIT 0x01
#define REQUEST_SENSE 0x03
#define FORMAT_UNIT 0x04
#define READ_BLOCK_LIMITS 0x05
#define REASSIGN_BLOCKS 0x07
#define READ_6 0x08
#define WRITE_6 0x0a
#define SEEK_6 0x0b
#define READ_REVERSE 0x0f
#define WRITE_FILEMARKS 0x10
#define SPACE 0x11
#define INQUIRY 0x12
#define RECOVER_BUFFERED_DATA 0x14
#define MODE_SELECT 0x15
#define RESERVE 0x16
#define RELEASE 0x17
#define COPY 0x18
#define ERASE 0x19
#define MODE_SENSE 0x1a
#define START_STOP 0x1b
#define RECEIVE_DIAGNOSTIC 0x1c
#define SEND_DIAGNOSTIC 0x1d
#define ALLOW_MEDIUM_REMOVAL 0x1e
#define SET_WINDOW 0x24
#define READ_CAPACITY 0x25
#define READ_10 0x28
#define WRITE_10 0x2a
#define SEEK_10 0x2b
#define WRITE_VERIFY 0x2e
#define VERIFY 0x2f
#define SEARCH_HIGH 0x30
#define SEARCH_EQUAL 0x31
#define SEARCH_LOW 0x32
#define SET_LIMITS 0x33
#define PRE_FETCH 0x34
#define READ_POSITION 0x34
#define SYNCHRONIZE_CACHE 0x35
#define LOCK_UNLOCK_CACHE 0x36
#define READ_DEFECT_DATA 0x37
#define MEDIUM_SCAN 0x38
#define COMPARE 0x39
#define COPY_VERIFY 0x3a
#define WRITE_BUFFER 0x3b
#define READ_BUFFER 0x3c
#define UPDATE_BLOCK 0x3d
#define READ_LONG 0x3e
#define WRITE_LONG 0x3f
#define CHANGE_DEFINITION 0x40
#define WRITE_SAME 0x41
#define READ_TOC 0x43
#define LOG_SELECT 0x4c
#define LOG_SENSE 0x4d
#define MODE_SELECT_10 0x55
#define RESERVE_10 0x56
#define RELEASE_10 0x57
#define MODE_SENSE_10 0x5a
#define PERSISTENT_RESERVE_IN 0x5e
#define PERSISTENT_RESERVE_OUT 0x5f
#define REPORT_LUNS 0xa0
#define MOVE_MEDIUM 0xa5
#define READ_12 0xa8
#define WRITE_12 0xaa
#define WRITE_VERIFY_12 0xae
#define SEARCH_HIGH_12 0xb0
#define SEARCH_EQUAL_12 0xb1
#define SEARCH_LOW_12 0xb2
#define READ_ELEMENT_STATUS 0xb8
#define SEND_VOLUME_TAG 0xb6
#define WRITE_LONG_2 0xea
#define READ_16 0x88
#define WRITE_16 0x8a
#define VERIFY_16 0x8f
#define SERVICE_ACTION_IN 0x9e
/* values for service action in */
#define SAI_READ_CAPACITY_16 0x10
#define SCSI_RETRY_10(c) ((c) == READ_6 || (c) == WRITE_6 || (c) == SEEK_6)
/*
* SCSI Architecture Model (SAM) Status codes. Taken from SAM-3 draft
* T10/1561-D Revision 4 Draft dated 7th November 2002.
*/
#define SAM_STAT_GOOD 0x00
#define SAM_STAT_CHECK_CONDITION 0x02
#define SAM_STAT_CONDITION_MET 0x04
#define SAM_STAT_BUSY 0x08
#define SAM_STAT_INTERMEDIATE 0x10
#define SAM_STAT_INTERMEDIATE_CONDITION_MET 0x14
#define SAM_STAT_RESERVATION_CONFLICT 0x18
#define SAM_STAT_COMMAND_TERMINATED 0x22 /* obsolete in SAM-3 */
#define SAM_STAT_TASK_SET_FULL 0x28
#define SAM_STAT_ACA_ACTIVE 0x30
#define SAM_STAT_TASK_ABORTED 0x40
/*
* Status codes
*/
#define GOOD 0x00
#define CHECK_CONDITION 0x01
#define CONDITION_GOOD 0x02
#define BUSY 0x04
#define INTERMEDIATE_GOOD 0x08
#define INTERMEDIATE_C_GOOD 0x0a
#define RESERVATION_CONFLICT 0x0c
#define COMMAND_TERMINATED 0x11
#define QUEUE_FULL 0x14
#define STATUS_MASK 0x3e
/*
* SENSE KEYS
*/
#define NO_SENSE 0x00
#define RECOVERED_ERROR 0x01
#define NOT_READY 0x02
#define MEDIUM_ERROR 0x03
#define HARDWARE_ERROR 0x04
#define ILLEGAL_REQUEST 0x05
#define UNIT_ATTENTION 0x06
#define DATA_PROTECT 0x07
#define BLANK_CHECK 0x08
#define COPY_ABORTED 0x0a
#define ABORTED_COMMAND 0x0b
#define VOLUME_OVERFLOW 0x0d
#define MISCOMPARE 0x0e
/*
* DEVICE TYPES
*/
#define TYPE_DISK 0x00
#define TYPE_TAPE 0x01
#define TYPE_PRINTER 0x02
#define TYPE_PROCESSOR 0x03 /* HP scanners use this */
#define TYPE_WORM 0x04 /* Treated as ROM by our system */
#define TYPE_ROM 0x05
#define TYPE_SCANNER 0x06
#define TYPE_MOD 0x07 /* Magneto-optical disk -
* - treated as TYPE_DISK */
#define TYPE_MEDIUM_CHANGER 0x08
#define TYPE_COMM 0x09 /* Communications device */
#define TYPE_ENCLOSURE 0x0d /* Enclosure Services Device */
#define TYPE_NO_LUN 0x7f
/*
* standard mode-select header prepended to all mode-select commands
*
* moved here from cdrom.h -- kraxel
*/
struct ccs_modesel_head
{
uint8_t _r1; /* reserved */
uint8_t medium; /* device-specific medium type */
uint8_t _r2; /* reserved */
uint8_t block_desc_length; /* block descriptor length */
uint8_t density; /* device-specific density code */
uint8_t number_blocks_hi; /* number of blocks in this block desc */
uint8_t number_blocks_med;
uint8_t number_blocks_lo;
uint8_t _r3;
uint8_t block_length_hi; /* block length for blocks in this desc */
uint8_t block_length_med;
uint8_t block_length_lo;
};
/*
* MESSAGE CODES
*/
#define COMMAND_COMPLETE 0x00
#define EXTENDED_MESSAGE 0x01
#define EXTENDED_MODIFY_DATA_POINTER 0x00
#define EXTENDED_SDTR 0x01
#define EXTENDED_EXTENDED_IDENTIFY 0x02 /* SCSI-I only */
#define EXTENDED_WDTR 0x03
#define SAVE_POINTERS 0x02
#define RESTORE_POINTERS 0x03
#define DISCONNECT 0x04
#define INITIATOR_ERROR 0x05
#define ABORT 0x06
#define MESSAGE_REJECT 0x07
#define NOP 0x08
#define MSG_PARITY_ERROR 0x09
#define LINKED_CMD_COMPLETE 0x0a
#define LINKED_FLG_CMD_COMPLETE 0x0b
#define BUS_DEVICE_RESET 0x0c
#define INITIATE_RECOVERY 0x0f /* SCSI-II only */
#define RELEASE_RECOVERY 0x10 /* SCSI-II only */
#define SIMPLE_QUEUE_TAG 0x20
#define HEAD_OF_QUEUE_TAG 0x21
#define ORDERED_QUEUE_TAG 0x22
/*
* Here are some scsi specific ioctl commands which are sometimes useful.
*/
/* These are a few other constants only used by scsi devices */
/* Note that include/linux/cdrom.h also defines IOCTL 0x5300 - 0x5395 */
#define SCSI_IOCTL_GET_IDLUN 0x5382 /* conflicts with CDROMAUDIOBUFSIZ */
/* Used to turn on and off tagged queuing for scsi devices */
#define SCSI_IOCTL_TAGGED_ENABLE 0x5383
#define SCSI_IOCTL_TAGGED_DISABLE 0x5384
/* Used to obtain the host number of a device. */
#define SCSI_IOCTL_PROBE_HOST 0x5385
/* Used to get the bus number for a device */
#define SCSI_IOCTL_GET_BUS_NUMBER 0x5386
/* Used to get the PCI location of a device */
#define SCSI_IOCTL_GET_PCI 0x5387
/*
* Overrides for Emacs so that we follow Linus's tabbing style.
* Emacs will notice this stuff at the end of the file and automatically
* adjust the settings for this buffer only. This must remain at the end
* of the file.
* ---------------------------------------------------------------------------
* Local variables:
* c-indent-level: 4
* c-brace-imaginary-offset: 0
* c-brace-offset: -4
* c-argdecl-indent: 4
* c-label-offset: -4
* c-continued-statement-offset: 4
* c-continued-brace-offset: 0
* indent-tabs-mode: nil
* tab-width: 8
* End:
*/
#endif

14
include/sparc32/crs.h
View File

@@ -12,17 +12,3 @@
#define AC_M_CXR 0x0200 /* shv Context Register */
#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
/*
* Parts of asm-sparc/contregs.h
*
* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
* space. These are for the mmu's context register, etc.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
#define AC_M_CXR 0x0200 /* shv Context Register */
#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */