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Create device tree according found PCI devices.

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Signed-off-by: Laurent Vivier <Laurent@lvivier.info>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/openbios/openbios-devel@257 f158a5a8-5612-0410-a976-696ce0be7e32
This commit is contained in:
Laurent Vivier
2008-11-24 12:29:36 +00:00
committed by Stefan Reinauer
parent ec800147a3
commit d6cd6543aa
3 changed files with 1390 additions and 173 deletions
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1497
drivers/pci.c
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File diff suppressed because it is too large Load Diff

5
drivers/pci.h
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@@ -4,6 +4,10 @@
#define PCI_VENDOR_ID 0x00
#define PCI_DEVICE_ID 0x02
#define PCI_COMMAND 0x04
#define PCI_COMMAND_IO 0x01
#define PCI_COMMAND_MEMORY 0x02
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
@@ -46,6 +50,7 @@
#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
#define PCI_MIN_GNT 0x3e /* 8 bits */
#define PCI_MAX_LAT 0x3f /* 8 bits */

43
include/ppc/pci.h
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@@ -3,15 +3,6 @@
#include "asm/io.h"
/* Sandpoint example */
#define ISA_IO_BASE 0x80000000
#define ISA_MEM_BASE 0xc0000000
#define PCIC0_CFGADDR 0xfec00cf8
#define PCIC0_CFGDATA 0xfee00cfc
#ifndef _IO_BASE
#define _IO_BASE ISA_IO_BASE
#endif
#if !(PCI_CONFIG_1 || PCI_CONFIG_2)
#define PCI_CONFIG_1 1 /* default */
#endif
@@ -20,10 +11,10 @@
/* PCI Configuration Mechanism #1 */
/* Have pci_addr in the same format as the values written to PCIC0_CFGADDR
* so register accesses can be made easy. */
extern pci_arch_t *arch;
#define PCI_ADDR(bus, dev, fn) \
((pci_addr) (0x80000000u \
((pci_addr) (arch->cfg_base \
| (uint32_t) (bus) << 16 \
| (uint32_t) (dev) << 11 \
| (uint32_t) (fn) << 8))
@@ -35,48 +26,44 @@
static inline uint8_t pci_config_read8(pci_addr dev, uint8_t reg)
{
uint8_t res;
out_le32((unsigned *)PCIC0_CFGADDR, (dev | (reg & ~3)));
res = in_8((unsigned char *)PCIC0_CFGDATA + (reg & 3));
out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
res = in_8((unsigned char*)(arch->cfg_data + (reg & 3)));
return res;
}
static inline uint16_t pci_config_read16(pci_addr dev, uint8_t reg)
{
uint16_t res;
out_le32((unsigned *)PCIC0_CFGADDR, (dev | (reg & ~3)));
res = in_le16((unsigned char *)PCIC0_CFGDATA + (reg & 2));
out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
res = in_le16((unsigned short*)(arch->cfg_data + (reg & 2)));
return res;
}
static inline uint32_t pci_config_read32(pci_addr dev, uint8_t reg)
{
uint32_t res;
out_le32((unsigned *)PCIC0_CFGADDR, (dev | (reg & ~3)));
res = in_le32((unsigned char *)PCIC0_CFGDATA);
out_le32((unsigned *)arch->cfg_addr, dev | reg);
res = in_le32((unsigned *)(arch->cfg_data + reg));
return res;
}
static inline void pci_config_write8(pci_addr dev, uint8_t reg, uint8_t val)
{
outl(dev | (reg & ~3), 0xcf8);
outb(val, 0xcfc | (reg & 3));
out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
out_8((unsigned char*)(arch->cfg_data + (reg & 3)), val);
}
static inline void pci_config_write16(pci_addr dev, uint8_t reg, uint16_t val)
{
outl(dev | (reg & ~3), 0xcf8);
outw(val, 0xcfc | (reg & 2));
out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
out_le16((unsigned short *)(arch->cfg_data + (reg & 2)), val);
}
static inline void pci_config_write32(pci_addr dev, uint8_t reg, uint32_t val)
{
outl(dev | reg, 0xcf8);
outl(val, 0xcfc);
out_le32((unsigned *)arch->cfg_addr, dev | reg);
out_le32((unsigned *)(arch->cfg_data + reg), val);
}
#else /* !PCI_CONFIG_1 */
#error PCI Configuration Mechanism is not specified or implemented
#endif