This patch originally started as a fix for PPC, in that the NVRAM initialiser wasn't been run on startup (this is why printenv
on PPC always showed much much less than on SPARC). However, it also showed up some inconsistent logic for boot device
selection, which must also happen *before* boot is called in order for load to work correctly. With this patch applied, bootpath
and bootargs are set from boot-device and boot-args respectively on startup for SPARC32, SPARC64 and PPC.
Note: there is a small chance SPARC32 may break on some images - please let me know if it does.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@siriusit.co.uk>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@805 f158a5a8-5612-0410-a976-696ce0be7e32
- sparc64 has PCI memory space at offset, therefore "ranges" property
of host bridge must have different PCI and host memory addresses
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@788 f158a5a8-5612-0410-a976-696ce0be7e32
- reformat to new style, no functional changes
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@787 f158a5a8-5612-0410-a976-696ce0be7e32
complete fix in that the VGA device is still present within the device tree, but it at least allows the bootloader and kernel to
execute far enough to prevent you from wondering why the console has apparently frozen.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@siriusit.co.uk>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@762 f158a5a8-5612-0410-a976-696ce0be7e32
disappears when booting a FC12 test ISO directly. Interestingly enough, if the equivalent "load" and "go" commands are entered
manually then the console output works fine and the ISO can boot?! So there is still an issue with the console not being
initialised correctly somewhere.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@siriusit.co.uk>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@734 f158a5a8-5612-0410-a976-696ce0be7e32
architectures are updated to use it. This is required to allow binding of C functions into Forth by libopenbios (i.e. cross
architecture) rather than having to update everything in every arch/*/ initialisation file.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@siriusit.co.uk>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@725 f158a5a8-5612-0410-a976-696ce0be7e32
configuration header file to include/arch/common. Following through the code showed that elfnote.c and linuxbios.c were being
used by sys_info and so these are also renamed to elf_info.c and linuxbios_info.c for clarity.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@siriusit.co.uk>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@693 f158a5a8-5612-0410-a976-696ce0be7e32
We changed the uninorth interrupt mapping to better reflect real
hardware. OpenBIOS obviously needs to know about that.
Signed-off-by: Alexander Graf <agraf@suse.de>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@682 f158a5a8-5612-0410-a976-696ce0be7e32
Linux on PPC64 knows only so many chipsets. One of the is the U3. So
we can use that when we're emulating a PPC64 machine, making Linux happy.
Signed-off-by: Alexander Graf <agraf@suse.de>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@681 f158a5a8-5612-0410-a976-696ce0be7e32
When running on Qemu (TCG) time goes by at a constant frequency which
accidently happens to match with Linux's fallback value.
As soon as we go to KVM, the time base suddenly starts going as fast as
the host CPU's time base. So we need to make sure Linux knows about
it, so it can do its timekeeping properly.
Signed-off-by: Alexander Graf <agraf@suse.de>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@678 f158a5a8-5612-0410-a976-696ce0be7e32
A real 970FX has more icache, so we should reflect that.
Signed-off-by: Alexander Graf <agraf@suse.de>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@677 f158a5a8-5612-0410-a976-696ce0be7e32
(allows Fedora bootloader to load the good kernel, 32-bit or 64-bit)
Signed-off-by: Laurent Vivier <Laurent@vivier.eu>
git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@607 f158a5a8-5612-0410-a976-696ce0be7e32
Expose PCI controller information
Linux tries to detect which PCI controller it's supposed to work with.
On PPC32 there is fallback code that doesn't get compiled with
CONFIG_PPC64, so we really have to expose a controller or we don't have
pci config space accessor functions.
Let's expose a un3-agp if we have a mac99 model, as that's what is
supposed to be in there anyways.
Signed-off-by: Alexander Graf <alex@csgraf.de>
Signed-off-by: Laurent Vivier <Laurent@vivier.eu>
git-svn-id: svn://coreboot.org/openbios/openbios-devel@466 f158a5a8-5612-0410-a976-696ce0be7e32
Expose NVRAM compatibility
Linux requires the NVRAM to expose a 'nvram,flash' compatibility
in the device tree. Let's expose it so it's happy.
v2 adds a NEWWORLD macro to protect nvram,flash getting exposed in
oldworld macs.
Signed-off-by: Alexander Graf <alex@csgraf.de>
Signed-off-by: Laurent Vivier <Laurent@vivier.eu>
git-svn-id: svn://coreboot.org/openbios/openbios-devel@465 f158a5a8-5612-0410-a976-696ce0be7e32
While booting a 64bit kernel, there is a small timeframe where OF and the kernel communicate with each other. Within that timeframe, DSI/ISI interrupts may occur, because some memory is not mapped yet.
Right now in case that happens, we jump into the DSI/ISI interrupt handler which clobbers the high 32 bits of the kernel's registers. In order to circumvent that, let's save/restore all 64 bits of all kernel registers when we get a DSI/ISI interrupt.
This patch enables a PPC64 Linux kernel to boot up to the point where it tries to set up the SLB entries (slbmte), which is not yet implemented in qemu.
v2 implements handling for the HIOR register, bringing interrupt handlers to RAM.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://coreboot.org/openbios/openbios-devel@462 f158a5a8-5612-0410-a976-696ce0be7e32
It gets up to the boot prompt and works rather good so far, though I haven't been able to run a kernel yet.
For more recent PowerPC CPUs the PTE layout has changed, so we need to take that into account and create PTEs according to the new layout and at the new physical positions.
Signed-off-by: Alexander Graf <alex@csgraf.de>
Signed-off-by: Laurent Vivier <Laurent@vivier.eu>
git-svn-id: svn://coreboot.org/openbios/openbios-devel@461 f158a5a8-5612-0410-a976-696ce0be7e32
and pciids.sourceforge.net.
Also fix a confusion between Sabre and Simba device IDs.
git-svn-id: svn://coreboot.org/openbios/openbios-devel@437 f158a5a8-5612-0410-a976-696ce0be7e32
If arch is ppc and machine arch id is heathrow, we create:
- properties in root node for a powermac beige
(Linux says "Powermac G3 (Silk)")
- "AAPL,interrupts" and "AAPL,address" properties in PCI device tree.
git-svn-id: svn://coreboot.org/openbios/openbios-devel@388 f158a5a8-5612-0410-a976-696ce0be7e32
This patches copies all needed ppc files to qemu and modifies them.
The generated OpenBIOS image must be loaded at adresse 0xfff00000 by Qemu.
It is able to load Yaboot from disk and Yaboot is able to load Linux, but Linux hangs somewhere... of course it needs more work (but this cleans up my patch queue).
Thank you to Blue Swirl and Aurelien Jarno for their help.
Signed-off-by: Laurent Vivier <Laurent@lvivier.info>
git-svn-id: svn://coreboot.org/openbios/openbios-devel@301 f158a5a8-5612-0410-a976-696ce0be7e32
Fix warnings that would be caused by gcc flag -Wwrite-strings and
-Wmissing-prototypes. Also fix most PPC specific warnings.
git-svn-id: svn://coreboot.org/openbios/openbios-devel@288 f158a5a8-5612-0410-a976-696ce0be7e32
