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https://gitlab.com/qemu-project/openbios.git
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1a3d4f52b4
git-svn-id: svn://coreboot.org/openbios/openbios-devel@209 f158a5a8-5612-0410-a976-696ce0be7e32
309 lines
7.5 KiB
ArmAsm
309 lines
7.5 KiB
ArmAsm
/**
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** Standalone startup code for Linux PROM emulator.
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** Copyright 1999 Pete A. Zaitcev
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** This code is licensed under GNU General Public License.
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**/
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/*
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* $Id: head.S,v 1.12 2002/07/23 05:47:09 zaitcev Exp $
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*/
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#define __ASSEMBLY__
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#include "asi.h"
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#include "pstate.h"
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#include "lsu.h"
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#define __ASSEMBLY__
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#include "openbios/firmware_abi.h"
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#define PROM_ADDR 0x1fff0000000
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.globl entry, _entry
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.section ".text", "ax"
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.align 8
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.register %g2, #scratch
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.register %g3, #scratch
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.register %g6, #scratch
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.register %g7, #scratch
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/*
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* Entry point
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* We start execution from here.
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*/
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_entry:
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entry:
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! Set up CPU state
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wrpr %g0, PSTATE_PRIV, %pstate
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wr %g0, 0, %fprs
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wrpr %g0, 0x0, %tl
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! Extract NWINDOWS from %ver
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rdpr %ver, %g1
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and %g1, 0xf, %g1
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dec %g1
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wrpr %g1, 0, %cleanwin
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wrpr %g1, 0, %cansave
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wrpr %g0, 0, %canrestore
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wrpr %g0, 0, %otherwin
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wrpr %g0, 0, %wstate
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! 100 Hz timer
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set 10 * 1000 * 1000, %g1
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wr %g1, 0, %tick_cmpr
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! Disable I/D MMUs and caches
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stxa %g0, [%g0] ASI_LSU_CONTROL
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! Get memory size from NVRAM
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setx 0x1fe02000074, %g2, %g5
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mov OHW_RAM_SIZE, %g2
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stba %g2, [%g5] ASI_PHYS_BYPASS_EC_E
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add %g5, 1, %g1
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stba %g0, [%g1] ASI_PHYS_BYPASS_EC_E
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add %g1, 2, %g1
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lduba [%g1] ASI_PHYS_BYPASS_EC_E, %g4
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sll %g4, 8, %g4
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inc %g2
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stba %g2, [%g5] ASI_PHYS_BYPASS_EC_E
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lduba [%g1] ASI_PHYS_BYPASS_EC_E, %g3
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or %g3, %g4, %g4
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sll %g4, 8, %g4
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inc %g2
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stba %g2, [%g5] ASI_PHYS_BYPASS_EC_E
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lduba [%g1] ASI_PHYS_BYPASS_EC_E, %g3
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or %g3, %g4, %g4
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sll %g4, 8, %g4
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inc %g2
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stba %g2, [%g5] ASI_PHYS_BYPASS_EC_E
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lduba [%g1] ASI_PHYS_BYPASS_EC_E, %g3
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or %g3, %g4, %g4
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sll %g4, 8, %g4
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inc %g2
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stba %g2, [%g5] ASI_PHYS_BYPASS_EC_E
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lduba [%g1] ASI_PHYS_BYPASS_EC_E, %g3
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or %g3, %g4, %g4
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sll %g4, 8, %g4
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inc %g2
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stba %g2, [%g5] ASI_PHYS_BYPASS_EC_E
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lduba [%g1] ASI_PHYS_BYPASS_EC_E, %g3
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or %g3, %g4, %g4
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sll %g4, 8, %g4
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inc %g2
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stba %g2, [%g5] ASI_PHYS_BYPASS_EC_E
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lduba [%g1] ASI_PHYS_BYPASS_EC_E, %g3
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or %g3, %g4, %g4
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sll %g4, 8, %g4
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inc %g2
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stba %g2, [%g5] ASI_PHYS_BYPASS_EC_E
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lduba [%g1] ASI_PHYS_BYPASS_EC_E, %g3
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or %g3, %g4, %g1
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! %g1 contains end of memory
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setx _end, %g7, %g3
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set 0xffff, %g2
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add %g3, %g2, %g3
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andn %g3, %g2, %g3
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setx _data, %g7, %g2
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sub %g3, %g2, %g2
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sub %g1, %g2, %g2 ! %g2 = start of private memory
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mov %g2, %l0
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! setup .data & .bss
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setx _data, %g7, %g4
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sub %g3, %g4, %g5
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srlx %g5, 16, %g6 ! %g6 = # of 64k .bss pages
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set 0xa0000000, %g3
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sllx %g3, 32, %g3
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or %g3, 0x76, %g3
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! valid, 64k, locked, cacheable(I/E/C), priv, writable
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set 48, %g7
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1: stxa %g4, [%g7] ASI_DMMU ! vaddr = _data + N * 0x10000, ctx=0
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or %g2, %g3, %g5
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! paddr = start_mem + N * 0x10000
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stxa %g5, [%g0] ASI_DTLB_DATA_IN
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set 0x10000, %g5
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add %g2, %g5, %g2
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add %g4, %g5, %g4
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deccc %g6
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bne 1b
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nop
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! setup .rodata, also make .text readable
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setx _data, %g7, %g5
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setx _start, %g7, %g4
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sub %g5, %g4, %g5
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srlx %g5, 16, %g6 ! %g6 = # of 64k .rodata pages
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set 48, %g7
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set 0x10000, %g5
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setx PROM_ADDR, %l1, %l2
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1: stxa %g4, [%g7] ASI_DMMU ! vaddr = _rodata, ctx=0
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set 0xa0000000, %g3
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sllx %g3, 32, %g3
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or %g3, 0x74, %g3
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or %l2, %g3, %g3
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! valid, 64k, locked, cacheable(I/E/C), priv
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! paddr = _rodata + N * 0x10000
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stxa %g3, [%g0] ASI_DTLB_DATA_IN
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add %g4, %g5, %g4
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deccc %g6
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bne 1b
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add %l2, %g5, %l2
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! setup VGA buffer
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setx 0x1ff004a0000, %g7, %g4
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mov 2, %g6
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set 48, %g7
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set 0x10000, %g5
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1: stxa %g4, [%g7] ASI_DMMU ! vaddr = 0x1ff004a0000, ctx=0
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set 0xa0000000, %g3
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sllx %g3, 32, %g3
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or %g3, 0x76, %g3
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or %g4, %g3, %g3
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! valid, 64k, locked, cacheable(I/E/C), priv, writable
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! paddr = 0x1ff004a0000
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stxa %g3, [%g0] ASI_DTLB_DATA_IN
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add %g4, %g5, %g4
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deccc %g6
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bne 1b
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nop
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#if 1
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! setup 0-16M
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mov %g0, %g4
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mov 4, %g6
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set 48, %g7
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set 0x400000, %g5
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1: stxa %g4, [%g7] ASI_DMMU ! vaddr = 0, ctx=0
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set 0xe0000000, %g3
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sllx %g3, 32, %g3
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or %g3, 0x36, %g3
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or %g4, %g3, %g3
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! valid, 4M, cacheable(I/E/C), priv, writable
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! paddr = 0
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stxa %g3, [%g0] ASI_DTLB_DATA_IN
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add %g4, %g5, %g4
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deccc %g6
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bne 1b
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nop
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#endif
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membar #Sync
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setx _start, %g7, %g4
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setx _rodata, %g7, %g5
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sub %g5, %g4, %g5
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srlx %g5, 16, %g6 ! %g6 = # of 64k .text pages
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set 0x10000, %g5
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set 48, %g7
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setx PROM_ADDR, %l1, %l2
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1: stxa %g4, [%g7] ASI_IMMU ! vaddr = _start, ctx=0
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set 0xa0000000, %g3
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sllx %g3, 32, %g3
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or %g3, 0x74, %g3
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or %l2, %g3, %g3
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! valid, 64k, locked, cacheable(I/E/C), priv
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! paddr = _start + N * 0x10000
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stxa %g3, [%g0] ASI_ITLB_DATA_IN
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add %g4, %g5, %g4
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deccc %g6
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bne 1b
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add %l2, %g5, %l2
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#if 1
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! setup 0-16M
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mov %g0, %g4
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mov 4, %g6
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set 0x400000, %g5
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1: stxa %g4, [%g7] ASI_IMMU ! vaddr = 0, ctx=0
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set 0xe0000000, %g3
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sllx %g3, 32, %g3
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or %g3, 0x34, %g3
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or %g4, %g3, %g3
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! valid, 4M, cacheable(I/E/C), priv
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! paddr = 0
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stxa %g3, [%g0] ASI_ITLB_DATA_IN
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add %g4, %g5, %g4
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deccc %g6
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bne 1b
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nop
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#endif
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flush %g4
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mov %g1, %g3
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set 8, %g2
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sta %g0, [%g2] ASI_DMMU ! set primary ctx=0
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! Enable I/D MMUs and caches
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setx lowmem, %g2, %g1
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set LSU_CONTROL_DM|LSU_CONTROL_IM|LSU_CONTROL_DC|LSU_CONTROL_IC, %g2
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jmp %g1
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stxa %g2, [%g0] ASI_LSU_CONTROL
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lowmem:
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/* Copy the DATA section from ROM. */
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setx _data - 8, %o7, %o0 ! First address of DATA
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setx _bss, %o7, %o1 ! Last address of DATA
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setx _start, %o7, %o2
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sub %o0, %o2, %o2 ! _data - _start
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setx PROM_ADDR, %o7, %o3
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add %o3, %o2, %o2 ! PROM_ADDR + (_data - _start)
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ba 2f
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nop
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1:
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ldxa [%o2] ASI_PHYS_BYPASS_EC_E, %g1
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stx %g1, [%o0]
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2:
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add %o2, 0x8, %o2
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subcc %o0, %o1, %g0
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bl 1b
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add %o0, 0x8, %o0
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/* Zero out our BSS section. */
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setx _bss - 8, %o7, %o0 ! First address of BSS
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setx _end - 8, %o7, %o1 ! Last address of BSS
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ba 2f
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nop
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1:
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stx %g0, [%o0]
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2:
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subcc %o0, %o1, %g0
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bl 1b
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add %o0, 0x8, %o0
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setx trap_table, %g2, %g1
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wrpr %g1, %tba
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setx qemu_mem_size, %g7, %g1
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stx %g3, [%g1]
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setx _data, %g7, %g1 ! Store va->pa conversion factor
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sub %g1, %l0, %g2
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setx va_shift, %g7, %g1
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stx %g2, [%g1]
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/* Finally, turn on traps so that we can call c-code. */
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wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
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/* Switch to our main context.
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* Main context is statically defined in C.
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*/
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call __switch_context_nosave
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nop
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/* We get here when the main context switches back to
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* the boot context.
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* Return to previous bootloader.
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*/
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ret
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nop
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