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853aec9291
Signed-off-by: igor.v.kovalenko@gmail.com git-svn-id: svn://coreboot.org/openbios/trunk/openbios-devel@507 f158a5a8-5612-0410-a976-696ce0be7e32
84 lines
2.6 KiB
C
84 lines
2.6 KiB
C
#ifndef PCI_H
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#define PCI_H
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#define PCI_VENDOR_ID 0x00
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#define PCI_DEVICE_ID 0x02
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#define PCI_COMMAND 0x04
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#define PCI_COMMAND_IO 0x01
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#define PCI_COMMAND_MEMORY 0x02
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#define PCI_STATUS 0x06 /* 16 bits */
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#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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#define PCI_STATUS_UDF 0x40 /* Support User Definable Features
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[obsolete] */
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#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
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#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
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#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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#define PCI_STATUS_DEVSEL_FAST 0x000
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#define PCI_STATUS_DEVSEL_MEDIUM 0x200
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#define PCI_STATUS_DEVSEL_SLOW 0x400
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#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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#define PCI_REVISION_ID 0x08 /* Revision ID */
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#define PCI_CLASS_PROG 0x09
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#define PCI_CLASS_DEVICE 0x0a
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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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#define PCI_HEADER_TYPE 0x0e
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#define PCI_HEADER_TYPE_NORMAL 0x00
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#define PCI_HEADER_TYPE_BRIDGE 0x01
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#define PCI_HEADER_TYPE_CARDBUS 0x02
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#define PCI_SECONDARY_BUS 0x19
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#define PCI_BASE_ADDR_0 0x10
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#define PCI_BASE_ADDR_1 0x14
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#define PCI_BASE_ADDR_2 0x18
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#define PCI_BASE_ADDR_3 0x1c
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#define PCI_BASE_ADDR_4 0x20
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#define PCI_BASE_ADDR_5 0x24
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#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
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#define PCI_SUBSYSTEM_ID 0x2e
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#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
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#define PCI_ROM_ADDRESS_ENABLE 0x01
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#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
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#define PCI_ROM_ADDRESS1 0x38 /* ROM_ADDRESS in bridge header */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_MIN_GNT 0x3e /* 8 bits */
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#define PCI_MAX_LAT 0x3f /* 8 bits */
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typedef struct {
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u16 signature;
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u8 reserved[0x16];
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u16 dptr;
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} rom_header_t;
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typedef struct {
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u32 signature;
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u16 vendor;
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u16 device;
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u16 reserved_1;
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u16 dlen;
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u8 drevision;
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u8 class_hi;
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u16 class_lo;
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u16 ilen;
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u16 irevision;
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u8 type;
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u8 indicator;
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u16 reserved_2;
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} pci_data_t;
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#include "asm/pci.h"
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#endif /* PCI_H */
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