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https://gitlab.com/qemu-project/openbios.git
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e774472da7
git-svn-id: svn://coreboot.org/openbios/openbios-devel@143 f158a5a8-5612-0410-a976-696ce0be7e32
318 lines
9.8 KiB
ArmAsm
318 lines
9.8 KiB
ArmAsm
/**
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** Standalone startup code for Linux PROM emulator.
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** Copyright 1999 Pete A. Zaitcev
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** This code is licensed under GNU General Public License.
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**/
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/*
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* $Id: head.S,v 1.12 2002/07/23 05:47:09 zaitcev Exp $
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*/
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#include "psr.h"
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#include "asi.h"
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#include "asm/crs.h"
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#define PHYS_JJ_EEPROM 0x71200000 /* [2000] MK48T08 */
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#define PHYS_JJ_INTR0 0x71E00000 /* CPU0 interrupt control registers */
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#define PHYS_SS10_EEPROM 0xf1200000 /* XXX Actually at 0xff1200000ULL (36 bits)*/
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#define PHYS_SS10_INTR0 0xf1400000 /* 0xff1400000ULL */
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#define WRITE_PAUSE nop; nop; nop; /* Have to do this after %wim/%psr chg */
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.globl entry, _entry
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.section ".text", "ax"
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.align 8
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/*
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* Entry point
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* We start execution from here.
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*/
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_entry:
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entry:
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/* Switch to our main context.
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* Main context is statically defined in C.
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*/
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! Check if this is QEMU for SS-5
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set PHYS_JJ_EEPROM, %g1
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lduba [%g1] ASI_M_BYPASS, %g2
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cmp %g2, 'Q'
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bne ss10
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inc %g1
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lduba [%g1] ASI_M_BYPASS, %g2
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cmp %g2, 'E'
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bne ss10
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inc %g1
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lduba [%g1] ASI_M_BYPASS, %g2
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cmp %g2, 'M'
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bne ss10
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inc %g1
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lduba [%g1] ASI_M_BYPASS, %g2
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cmp %g2, 'U'
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bne ss10
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! Ok, this is SS-5
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mov 0x80, %y
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! Check if this not the first SMP CPU, if so, bypass PROM entirely
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set PHYS_JJ_EEPROM + 0x2E, %g1
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lduba [%g1] ASI_M_BYPASS, %g2
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set PHYS_JJ_EEPROM + 0x30, %g1
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tst %g2
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bz first_cpu
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nop
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set PHYS_JJ_INTR0 + 0x04, %g1
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sll %g2, 12, %g2
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add %g1, %g2, %g2
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set 0xffffffff, %g1
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sta %g1, [%g2] ASI_M_BYPASS ! clear softints
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add %g2, 4, %g2
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sta %g0, [%g2] ASI_M_BYPASS ! clear softints
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set PHYS_JJ_EEPROM + 0x3C, %g1
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lda [%g1] ASI_M_BYPASS, %g1
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set AC_M_CTPR, %g2
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sta %g1, [%g2] ASI_M_MMUREGS ! set ctx table ptr
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set PHYS_JJ_EEPROM + 0x40, %g1
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lda [%g1] ASI_M_BYPASS, %g1
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set AC_M_CXR, %g2
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sta %g1, [%g2] ASI_M_MMUREGS ! set context
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set PHYS_JJ_EEPROM + 0x38, %g1
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lda [%g1] ASI_M_BYPASS, %g2
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set 1, %g1
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jmp %g2 ! jump to kernel
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sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu
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bad_nvram:
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! Unknown machine, freeze
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b bad_nvram
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nop
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ss10:
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set PHYS_SS10_EEPROM, %g1
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! XXX use full 36 bits access
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lduba [%g1] ASI_M_BYPASS, %g2
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cmp %g2, 'Q'
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bne bad_nvram
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inc %g1
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lduba [%g1] ASI_M_BYPASS, %g2
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cmp %g2, 'E'
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bne bad_nvram
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inc %g1
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lduba [%g1] ASI_M_BYPASS, %g2
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cmp %g2, 'M'
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bne bad_nvram
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inc %g1
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lduba [%g1] ASI_M_BYPASS, %g2
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cmp %g2, 'U'
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bne bad_nvram
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! Ok, this is SS-10
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mov 0x72, %y
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! Check if this not the first SMP CPU, if so, bypass PROM entirely
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! XXX use full 36 bits access
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set PHYS_SS10_EEPROM + 0x2E, %g1
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lduba [%g1] ASI_M_BYPASS, %g2
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set PHYS_SS10_EEPROM + 0x30, %g1
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tst %g2
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bz first_cpu
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nop
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set PHYS_SS10_INTR0 + 0x04, %g1
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sll %g2, 12, %g2
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add %g1, %g2, %g2
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set 0xffffffff, %g1
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sta %g1, [%g2] ASI_M_BYPASS ! clear softints
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add %g2, 4, %g2
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sta %g0, [%g2] ASI_M_BYPASS ! clear softints
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set PHYS_SS10_EEPROM + 0x3C, %g1
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lda [%g1] ASI_M_BYPASS, %g1
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set AC_M_CTPR, %g2
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sta %g1, [%g2] ASI_M_MMUREGS ! set ctx table ptr
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set PHYS_JJ_EEPROM + 0x40, %g1
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lda [%g1] ASI_M_BYPASS, %g1
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set AC_M_CXR, %g2
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sta %g1, [%g2] ASI_M_MMUREGS ! set context
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set PHYS_SS10_EEPROM + 0x38, %g1
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lda [%g1] ASI_M_BYPASS, %g2
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set 1, %g1
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jmp %g2 ! jump to kernel
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sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu
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first_cpu:
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/* Create temporary page tables and map the ROM area to end of
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RAM. This will be done properly in iommu.c later. */
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lda [%g1] ASI_M_BYPASS, %g1
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set _end, %g3
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set 0xfff, %g2
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add %g3, %g2, %g3
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andn %g3, %g2, %g3
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set _start, %g2
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sub %g3, %g2, %g3
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set 0x1000, %g4 ! add 0x1000 for page tables
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add %g4, %g3, %g2
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sub %g1, %g2, %g2 ! start of private memory
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srl %g2, 0x4, %g7 ! ctx table at s+0x0
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add %g2, 0x400, %g3 ! l1 table at s+0x400
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 0x400, %g2 ! s+0x400
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add %g2, 0x400, %g3 ! l2 table for ram (00xxxxxx) at s+0x800
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 0x500, %g3 ! l2 table for rom (ffxxxxxx) at s+0x900
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add %g2, 0x3fc, %g2 ! s+0x7fc
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 0x4, %g2 ! s+0x800
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#if 0
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set 0x40, %g6
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set ((7 << 2) | 2), %g3 ! 7 = U: --- S: RWX (main memory)
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1: sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2
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deccc %g6
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bne 1b
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nop
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#else
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add %g2, 0x100, %g2
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#endif
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! s+0x900
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add %g2, 0xa00 - 0x900, %g3 ! l3 table for rom at s+0xa00
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add %g2, 0x0d0, %g2 ! s+0x9d0
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9d4
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add %g2, 0xb00 - 0x9d4, %g3 ! 2nd l3 table for rom at s+0xb00
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9d8
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add %g2, 0xc00 - 0x9d8, %g3 ! 3rd l3 table for rom at s+0xc00
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9dc
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add %g2, 0xd00 - 0x9dc, %g3 ! 4th l3 table for rom at s+0xd00
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2 ! s+0x9e0
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add %g2, 0xd00 - 0x9e0, %g3 ! 5th l3 table for rom at s+0xe00
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srl %g3, 0x4, %g3
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or %g3, 0x1, %g3
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sta %g3, [%g2] ASI_M_BYPASS
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add %g2, 0xa00-0x9e0, %g2 ! s+0xa00
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/* Use end of ram for code, rodata, data, and bss
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sections. SunOS wants to write to trap table... */
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set _end, %g6
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set _start, %g4
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sub %g6, %g4, %g6
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srl %g6, 12, %g6 ! # of all pages
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set 0x1000, %g5
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sll %g7, 0x4, %g3
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add %g5, %g3, %g3 ! ctx table + 0x1000
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1: srl %g3, 0x4, %g4
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or %g4, ((7 << 2) | 2), %g4 ! 7 = U: --- S: RWX
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sta %g4, [%g2] ASI_M_BYPASS
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add %g2, 4, %g2
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add %g3, %g5, %g3
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deccc %g6
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bne 1b
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nop
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mov %g1, %g6 ! %g6 = memory size
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/* Copy the code, rodata and data sections from ROM. */
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set 0x1000 - 4, %g4
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sll %g7, 0x4, %g3
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add %g4, %g3, %g3 ! ctx table + 0x1000 - 4
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set _start - 4, %g4 ! First address of TEXT
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set _bss, %g5 ! Last address of DATA
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ba 2f
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nop
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1:
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lda [%g4] ASI_M_BYPASS, %g1
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sta %g1, [%g3] ASI_M_BYPASS
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2:
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cmp %g4, %g5
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add %g3, 0x4, %g3
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bl 1b
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add %g4, 0x4, %g4
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set AC_M_CTPR, %g2
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sta %g7, [%g2] ASI_M_MMUREGS ! set ctx table ptr
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set AC_M_CXR, %g2
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sta %g0, [%g2] ASI_M_MMUREGS ! context 0
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set 1, %g1
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sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu
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/*
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* The code which enables traps is a simplified version of
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* kernel head.S.
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*
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* We know number of windows as 8 so we do not calculate them.
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* The deadwood is here for any case.
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*/
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/* Turn on Supervisor, EnableFloating, and all the PIL bits.
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* Also puts us in register window zero with traps off.
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*/
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set (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
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wr %g2, 0x0, %psr
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WRITE_PAUSE
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/* Zero out our BSS section. */
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set _bss - 4, %o0 ! First address of BSS
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set _estack - 4, %o1 ! Last address of BSS
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ba 2f
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nop
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1:
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st %g0, [%o0]
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2:
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subcc %o0, %o1, %g0
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bl 1b
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add %o0, 0x4, %o0
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mov 2, %g1
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wr %g1, 0x0, %wim ! make window 1 invalid
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WRITE_PAUSE
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set trap_table, %g1
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wr %g1, 0x0, %tbr
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set qemu_mem_size, %g1
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st %g6, [%g1]
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sll %g7, 4, %g7 ! Store va->pa conversion factor
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set _start - 0x1000, %g1
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sub %g1, %g7, %g7
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set va_shift, %g1
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st %g7, [%g1]
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set qemu_machine_type, %g1
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mov %y, %g2
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st %g2, [%g1]
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/* Finally, turn on traps so that we can call c-code. */
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rd %psr, %g3
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wr %g3, 0x0, %psr
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WRITE_PAUSE
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wr %g3, PSR_ET, %psr
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WRITE_PAUSE
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call __switch_context_nosave
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nop
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/* We get here when the main context switches back to
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* the boot context.
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* Return to previous bootloader.
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*/
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ret
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nop
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