2018-12-11 21:54:06 +08:00
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/*
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2019-01-24 14:11:10 +08:00
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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2018-12-11 21:54:06 +08:00
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __RISCV_ENCODING_H__
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#define __RISCV_ENCODING_H__
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#include <sbi/sbi_const.h>
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/* TODO: Make constants usable in assembly with _AC() macro */
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2019-04-11 08:41:46 +08:00
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/* clang-format off */
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2018-12-11 21:54:06 +08:00
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#define MSTATUS_UIE 0x00000001
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#define MSTATUS_SIE 0x00000002
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#define MSTATUS_HIE 0x00000004
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#define MSTATUS_MIE 0x00000008
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#define MSTATUS_UPIE 0x00000010
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2018-12-28 00:09:13 +08:00
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#define MSTATUS_SPIE_SHIFT 5
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#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT)
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2018-12-11 21:54:06 +08:00
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#define MSTATUS_HPIE 0x00000040
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#define MSTATUS_MPIE 0x00000080
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2018-12-28 00:09:13 +08:00
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#define MSTATUS_SPP_SHIFT 8
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#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT)
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2018-12-11 21:54:06 +08:00
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#define MSTATUS_HPP 0x00000600
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2018-12-28 00:09:13 +08:00
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#define MSTATUS_MPP_SHIFT 11
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#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT)
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2018-12-11 21:54:06 +08:00
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#define MSTATUS_FS 0x00006000
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#define MSTATUS_XS 0x00018000
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#define MSTATUS_MPRV 0x00020000
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#define MSTATUS_SUM 0x00040000
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#define MSTATUS_MXR 0x00080000
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#define MSTATUS_TVM 0x00100000
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#define MSTATUS_TW 0x00200000
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#define MSTATUS_TSR 0x00400000
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#define MSTATUS32_SD 0x80000000
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2019-04-05 16:38:57 +08:00
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#if __riscv_xlen == 64
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2018-12-11 21:54:06 +08:00
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#define MSTATUS_UXL 0x0000000300000000
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#define MSTATUS_SXL 0x0000000C00000000
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2019-04-05 16:38:57 +08:00
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#define MSTATUS_MTL 0x0000004000000000
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#define MSTATUS_MTL_SHIFT 38
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#define MSTATUS_MPV 0x0000008000000000
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#define MSTATUS_MPV_HIFT 39
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#else
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#define MSTATUSH_UXL 0x00000003
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#define MSTATUSH_SXL 0x0000000C
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#define MSTATUSH_MTL 0x00000040
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#define MSTATUSH_MTL_SHIFT 6
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#define MSTATUSH_MPV 0x00000080
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#define MSTATUSH_MPV_HIFT 7
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#endif
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2018-12-11 21:54:06 +08:00
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#define MSTATUS64_SD 0x8000000000000000
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#define SSTATUS_UIE 0x00000001
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#define SSTATUS_SIE 0x00000002
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#define SSTATUS_UPIE 0x00000010
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2019-04-15 14:23:31 +08:00
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#define SSTATUS_SPIE_SHIFT 5
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#define SSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT)
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#define SSTATUS_SPP_SHIFT 8
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#define SSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT)
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2018-12-11 21:54:06 +08:00
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#define SSTATUS_FS 0x00006000
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#define SSTATUS_XS 0x00018000
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#define SSTATUS_SUM 0x00040000
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#define SSTATUS_MXR 0x00080000
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#define SSTATUS32_SD 0x80000000
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#define SSTATUS_UXL 0x0000000300000000
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#define SSTATUS64_SD 0x8000000000000000
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2019-04-15 14:23:31 +08:00
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#define HSTATUS_VTSR 0x00400000
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#define HSTATUS_VTVM 0x00100000
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#define HSTATUS_SP2V 0x00000200
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#define HSTATUS_SP2P 0x00000100
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#define HSTATUS_SPV 0x00000080
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#define HSTATUS_STL 0x00000040
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#define HSTATUS_SPRV 0x00000001
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2018-12-11 21:54:06 +08:00
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#define DCSR_XDEBUGVER (3U<<30)
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#define DCSR_NDRESET (1<<29)
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#define DCSR_FULLRESET (1<<28)
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#define DCSR_EBREAKM (1<<15)
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#define DCSR_EBREAKH (1<<14)
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#define DCSR_EBREAKS (1<<13)
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#define DCSR_EBREAKU (1<<12)
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#define DCSR_STOPCYCLE (1<<10)
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#define DCSR_STOPTIME (1<<9)
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#define DCSR_CAUSE (7<<6)
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#define DCSR_DEBUGINT (1<<5)
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#define DCSR_HALT (1<<3)
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#define DCSR_STEP (1<<2)
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#define DCSR_PRV (3<<0)
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#define DCSR_CAUSE_NONE 0
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#define DCSR_CAUSE_SWBP 1
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#define DCSR_CAUSE_HWBP 2
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#define DCSR_CAUSE_DEBUGINT 3
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#define DCSR_CAUSE_STEP 4
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#define DCSR_CAUSE_HALT 5
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#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
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#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
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#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
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#define MCONTROL_SELECT (1<<19)
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#define MCONTROL_TIMING (1<<18)
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#define MCONTROL_ACTION (0x3f<<12)
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#define MCONTROL_CHAIN (1<<11)
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#define MCONTROL_MATCH (0xf<<7)
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#define MCONTROL_M (1<<6)
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#define MCONTROL_H (1<<5)
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#define MCONTROL_S (1<<4)
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#define MCONTROL_U (1<<3)
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#define MCONTROL_EXECUTE (1<<2)
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#define MCONTROL_STORE (1<<1)
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#define MCONTROL_LOAD (1<<0)
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#define MCONTROL_TYPE_NONE 0
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#define MCONTROL_TYPE_MATCH 2
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#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
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#define MCONTROL_ACTION_DEBUG_MODE 1
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#define MCONTROL_ACTION_TRACE_START 2
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#define MCONTROL_ACTION_TRACE_STOP 3
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#define MCONTROL_ACTION_TRACE_EMIT 4
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#define MCONTROL_MATCH_EQUAL 0
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#define MCONTROL_MATCH_NAPOT 1
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#define MCONTROL_MATCH_GE 2
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#define MCONTROL_MATCH_LT 3
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#define MCONTROL_MATCH_MASK_LOW 4
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#define MCONTROL_MATCH_MASK_HIGH 5
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#define IRQ_S_SOFT 1
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#define IRQ_H_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_H_TIMER 6
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_H_EXT 10
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#define IRQ_M_EXT 11
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#define IRQ_COP 12
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#define IRQ_HOST 13
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#define MIP_SSIP (1 << IRQ_S_SOFT)
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#define MIP_HSIP (1 << IRQ_H_SOFT)
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#define MIP_MSIP (1 << IRQ_M_SOFT)
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#define MIP_STIP (1 << IRQ_S_TIMER)
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#define MIP_HTIP (1 << IRQ_H_TIMER)
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#define MIP_MTIP (1 << IRQ_M_TIMER)
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#define MIP_SEIP (1 << IRQ_S_EXT)
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#define MIP_HEIP (1 << IRQ_H_EXT)
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#define MIP_MEIP (1 << IRQ_M_EXT)
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#define SIP_SSIP MIP_SSIP
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#define SIP_STIP MIP_STIP
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#define PRV_U 0
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#define PRV_S 1
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#define PRV_H 2
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#define PRV_M 3
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#define SATP32_MODE 0x80000000
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#define SATP32_ASID 0x7FC00000
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#define SATP32_PPN 0x003FFFFF
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#define SATP64_MODE 0xF000000000000000
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#define SATP64_ASID 0x0FFFF00000000000
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#define SATP64_PPN 0x00000FFFFFFFFFFF
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#define SATP_MODE_OFF 0
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#define SATP_MODE_SV32 1
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#define SATP_MODE_SV39 8
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#define SATP_MODE_SV48 9
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#define SATP_MODE_SV57 10
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#define SATP_MODE_SV64 11
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#define PMP_R 0x01
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#define PMP_W 0x02
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#define PMP_X 0x04
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#define PMP_A 0x18
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#define PMP_A_TOR 0x08
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#define PMP_A_NA4 0x10
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#define PMP_A_NAPOT 0x18
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#define PMP_L 0x80
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#define PMP_SHIFT 2
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#define PMP_COUNT 16
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/* page table entry (PTE) fields */
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#define PTE_V 0x001 /* Valid */
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#define PTE_R 0x002 /* Read */
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#define PTE_W 0x004 /* Write */
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#define PTE_X 0x008 /* Execute */
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#define PTE_U 0x010 /* User */
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#define PTE_G 0x020 /* Global */
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#define PTE_A 0x040 /* Accessed */
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#define PTE_D 0x080 /* Dirty */
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#define PTE_SOFT 0x300 /* Reserved for Software */
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#define PTE_PPN_SHIFT 10
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#define PTE_TABLE(PTE) \
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(((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
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#if __riscv_xlen == 64
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#define MSTATUS_SD MSTATUS64_SD
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#define SSTATUS_SD SSTATUS64_SD
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#define RISCV_PGLEVEL_BITS 9
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#define SATP_MODE SATP64_MODE
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#else
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#define MSTATUS_SD MSTATUS32_SD
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#define SSTATUS_SD SSTATUS32_SD
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#define RISCV_PGLEVEL_BITS 10
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#define SATP_MODE SATP32_MODE
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#endif
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#define RISCV_PGSHIFT 12
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#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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2019-02-13 10:32:06 +08:00
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#define CSR_USTATUS 0x0
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2018-12-11 21:54:06 +08:00
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#define CSR_FFLAGS 0x1
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#define CSR_FRM 0x2
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#define CSR_FCSR 0x3
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#define CSR_CYCLE 0xc00
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2019-02-13 10:32:06 +08:00
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#define CSR_UIE 0x4
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#define CSR_UTVEC 0x5
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#define CSR_USCRATCH 0x40
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#define CSR_UEPC 0x41
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#define CSR_UCAUSE 0x42
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#define CSR_UTVAL 0x43
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#define CSR_UIP 0x44
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2018-12-11 21:54:06 +08:00
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#define CSR_TIME 0xc01
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#define CSR_INSTRET 0xc02
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#define CSR_HPMCOUNTER3 0xc03
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#define CSR_HPMCOUNTER4 0xc04
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#define CSR_HPMCOUNTER5 0xc05
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#define CSR_HPMCOUNTER6 0xc06
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#define CSR_HPMCOUNTER7 0xc07
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#define CSR_HPMCOUNTER8 0xc08
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#define CSR_HPMCOUNTER9 0xc09
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#define CSR_HPMCOUNTER10 0xc0a
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#define CSR_HPMCOUNTER11 0xc0b
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#define CSR_HPMCOUNTER12 0xc0c
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#define CSR_HPMCOUNTER13 0xc0d
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#define CSR_HPMCOUNTER14 0xc0e
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#define CSR_HPMCOUNTER15 0xc0f
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#define CSR_HPMCOUNTER16 0xc10
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#define CSR_HPMCOUNTER17 0xc11
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#define CSR_HPMCOUNTER18 0xc12
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#define CSR_HPMCOUNTER19 0xc13
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#define CSR_HPMCOUNTER20 0xc14
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#define CSR_HPMCOUNTER21 0xc15
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#define CSR_HPMCOUNTER22 0xc16
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#define CSR_HPMCOUNTER23 0xc17
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#define CSR_HPMCOUNTER24 0xc18
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#define CSR_HPMCOUNTER25 0xc19
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#define CSR_HPMCOUNTER26 0xc1a
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#define CSR_HPMCOUNTER27 0xc1b
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#define CSR_HPMCOUNTER28 0xc1c
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#define CSR_HPMCOUNTER29 0xc1d
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#define CSR_HPMCOUNTER30 0xc1e
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#define CSR_HPMCOUNTER31 0xc1f
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#define CSR_SSTATUS 0x100
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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#define CSR_SATP 0x180
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2019-04-15 14:23:31 +08:00
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#define CSR_HSTATUS 0x600
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#define CSR_HEDELEG 0x602
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#define CSR_HIDELEG 0x603
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#define CSR_HCOUNTERNEN 0x606
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#define CSR_HGATP 0x680
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#define CSR_VSSTATUS 0x200
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#define CSR_VSIE 0x204
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#define CSR_VSTVEC 0x205
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#define CSR_VSSCRATCH 0x240
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#define CSR_VSEPC 0x241
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#define CSR_VSCAUSE 0x242
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#define CSR_VSTVAL 0x243
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#define CSR_VSIP 0x244
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#define CSR_VSATP 0x280
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2018-12-11 21:54:06 +08:00
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MEDELEG 0x302
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#define CSR_MIDELEG 0x303
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MCOUNTEREN 0x306
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2019-04-05 16:38:57 +08:00
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#define CSR_MSTATUSH 0x310
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2018-12-11 21:54:06 +08:00
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPCFG1 0x3a1
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#define CSR_PMPCFG2 0x3a2
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#define CSR_PMPCFG3 0x3a3
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#define CSR_PMPADDR0 0x3b0
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#define CSR_PMPADDR1 0x3b1
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#define CSR_PMPADDR2 0x3b2
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#define CSR_PMPADDR3 0x3b3
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#define CSR_PMPADDR4 0x3b4
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#define CSR_PMPADDR5 0x3b5
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#define CSR_PMPADDR6 0x3b6
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#define CSR_PMPADDR7 0x3b7
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#define CSR_PMPADDR8 0x3b8
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#define CSR_PMPADDR9 0x3b9
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#define CSR_PMPADDR10 0x3ba
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#define CSR_PMPADDR11 0x3bb
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#define CSR_PMPADDR12 0x3bc
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#define CSR_PMPADDR13 0x3bd
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#define CSR_PMPADDR14 0x3be
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#define CSR_PMPADDR15 0x3bf
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#define CSR_TSELECT 0x7a0
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#define CSR_TDATA1 0x7a1
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#define CSR_TDATA2 0x7a2
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#define CSR_TDATA3 0x7a3
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#define CSR_DCSR 0x7b0
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#define CSR_DPC 0x7b1
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#define CSR_DSCRATCH 0x7b2
|
2019-04-15 14:23:31 +08:00
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2018-12-11 21:54:06 +08:00
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#define CSR_MCYCLE 0xb00
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#define CSR_MINSTRET 0xb02
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#define CSR_MHPMCOUNTER3 0xb03
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#define CSR_MHPMCOUNTER4 0xb04
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#define CSR_MHPMCOUNTER5 0xb05
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#define CSR_MHPMCOUNTER6 0xb06
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#define CSR_MHPMCOUNTER7 0xb07
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#define CSR_MHPMCOUNTER8 0xb08
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#define CSR_MHPMCOUNTER9 0xb09
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#define CSR_MHPMCOUNTER10 0xb0a
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#define CSR_MHPMCOUNTER11 0xb0b
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#define CSR_MHPMCOUNTER12 0xb0c
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#define CSR_MHPMCOUNTER13 0xb0d
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#define CSR_MHPMCOUNTER14 0xb0e
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#define CSR_MHPMCOUNTER15 0xb0f
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#define CSR_MHPMCOUNTER16 0xb10
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#define CSR_MHPMCOUNTER17 0xb11
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#define CSR_MHPMCOUNTER18 0xb12
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#define CSR_MHPMCOUNTER19 0xb13
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#define CSR_MHPMCOUNTER20 0xb14
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#define CSR_MHPMCOUNTER21 0xb15
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#define CSR_MHPMCOUNTER22 0xb16
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#define CSR_MHPMCOUNTER23 0xb17
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#define CSR_MHPMCOUNTER24 0xb18
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#define CSR_MHPMCOUNTER25 0xb19
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#define CSR_MHPMCOUNTER26 0xb1a
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#define CSR_MHPMCOUNTER27 0xb1b
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#define CSR_MHPMCOUNTER28 0xb1c
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#define CSR_MHPMCOUNTER29 0xb1d
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#define CSR_MHPMCOUNTER30 0xb1e
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#define CSR_MHPMCOUNTER31 0xb1f
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#define CSR_MHPMEVENT3 0x323
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#define CSR_MHPMEVENT4 0x324
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#define CSR_MHPMEVENT5 0x325
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#define CSR_MHPMEVENT6 0x326
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#define CSR_MHPMEVENT7 0x327
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#define CSR_MHPMEVENT8 0x328
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#define CSR_MHPMEVENT9 0x329
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#define CSR_MHPMEVENT10 0x32a
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#define CSR_MHPMEVENT11 0x32b
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#define CSR_MHPMEVENT12 0x32c
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#define CSR_MHPMEVENT13 0x32d
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#define CSR_MHPMEVENT14 0x32e
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#define CSR_MHPMEVENT15 0x32f
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#define CSR_MHPMEVENT16 0x330
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#define CSR_MHPMEVENT17 0x331
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#define CSR_MHPMEVENT18 0x332
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#define CSR_MHPMEVENT19 0x333
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#define CSR_MHPMEVENT20 0x334
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#define CSR_MHPMEVENT21 0x335
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#define CSR_MHPMEVENT22 0x336
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#define CSR_MHPMEVENT23 0x337
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#define CSR_MHPMEVENT24 0x338
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#define CSR_MHPMEVENT25 0x339
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#define CSR_MHPMEVENT26 0x33a
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#define CSR_MHPMEVENT27 0x33b
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#define CSR_MHPMEVENT28 0x33c
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#define CSR_MHPMEVENT29 0x33d
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#define CSR_MHPMEVENT30 0x33e
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#define CSR_MHPMEVENT31 0x33f
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#define CSR_MVENDORID 0xf11
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#define CSR_MARCHID 0xf12
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#define CSR_MIMPID 0xf13
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#define CSR_MHARTID 0xf14
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#define CSR_HPMCOUNTER3H 0xc83
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#define CSR_HPMCOUNTER4H 0xc84
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#define CSR_HPMCOUNTER5H 0xc85
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#define CSR_HPMCOUNTER6H 0xc86
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#define CSR_HPMCOUNTER7H 0xc87
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#define CSR_HPMCOUNTER8H 0xc88
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#define CSR_HPMCOUNTER9H 0xc89
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#define CSR_HPMCOUNTER10H 0xc8a
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#define CSR_HPMCOUNTER11H 0xc8b
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#define CSR_HPMCOUNTER12H 0xc8c
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#define CSR_HPMCOUNTER13H 0xc8d
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#define CSR_HPMCOUNTER14H 0xc8e
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#define CSR_HPMCOUNTER15H 0xc8f
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#define CSR_HPMCOUNTER16H 0xc90
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#define CSR_HPMCOUNTER17H 0xc91
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#define CSR_HPMCOUNTER18H 0xc92
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#define CSR_HPMCOUNTER19H 0xc93
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#define CSR_HPMCOUNTER20H 0xc94
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#define CSR_HPMCOUNTER21H 0xc95
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#define CSR_HPMCOUNTER22H 0xc96
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#define CSR_HPMCOUNTER23H 0xc97
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#define CSR_HPMCOUNTER24H 0xc98
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#define CSR_HPMCOUNTER25H 0xc99
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#define CSR_HPMCOUNTER26H 0xc9a
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#define CSR_HPMCOUNTER27H 0xc9b
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#define CSR_HPMCOUNTER28H 0xc9c
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#define CSR_HPMCOUNTER29H 0xc9d
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#define CSR_HPMCOUNTER30H 0xc9e
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#define CSR_HPMCOUNTER31H 0xc9f
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#define CSR_MCYCLEH 0xb80
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|
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#define CSR_MINSTRETH 0xb82
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#define CSR_MHPMCOUNTER3H 0xb83
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#define CSR_MHPMCOUNTER4H 0xb84
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#define CSR_MHPMCOUNTER5H 0xb85
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#define CSR_MHPMCOUNTER6H 0xb86
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#define CSR_MHPMCOUNTER7H 0xb87
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#define CSR_MHPMCOUNTER8H 0xb88
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#define CSR_MHPMCOUNTER9H 0xb89
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#define CSR_MHPMCOUNTER10H 0xb8a
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#define CSR_MHPMCOUNTER11H 0xb8b
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#define CSR_MHPMCOUNTER12H 0xb8c
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#define CSR_MHPMCOUNTER13H 0xb8d
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#define CSR_MHPMCOUNTER14H 0xb8e
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#define CSR_MHPMCOUNTER15H 0xb8f
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#define CSR_MHPMCOUNTER16H 0xb90
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#define CSR_MHPMCOUNTER17H 0xb91
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#define CSR_MHPMCOUNTER18H 0xb92
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#define CSR_MHPMCOUNTER19H 0xb93
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#define CSR_MHPMCOUNTER20H 0xb94
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#define CSR_MHPMCOUNTER21H 0xb95
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#define CSR_MHPMCOUNTER22H 0xb96
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#define CSR_MHPMCOUNTER23H 0xb97
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#define CSR_MHPMCOUNTER24H 0xb98
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#define CSR_MHPMCOUNTER25H 0xb99
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#define CSR_MHPMCOUNTER26H 0xb9a
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#define CSR_MHPMCOUNTER27H 0xb9b
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#define CSR_MHPMCOUNTER28H 0xb9c
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#define CSR_MHPMCOUNTER29H 0xb9d
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#define CSR_MHPMCOUNTER30H 0xb9e
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#define CSR_MHPMCOUNTER31H 0xb9f
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|
#define CAUSE_MISALIGNED_FETCH 0x0
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|
|
#define CAUSE_FETCH_ACCESS 0x1
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|
|
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
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|
|
#define CAUSE_BREAKPOINT 0x3
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|
|
#define CAUSE_MISALIGNED_LOAD 0x4
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|
|
#define CAUSE_LOAD_ACCESS 0x5
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|
|
#define CAUSE_MISALIGNED_STORE 0x6
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|
|
#define CAUSE_STORE_ACCESS 0x7
|
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|
|
#define CAUSE_USER_ECALL 0x8
|
2019-04-06 05:05:15 +08:00
|
|
|
#define CAUSE_HYPERVISOR_ECALL 0x9
|
|
|
|
#define CAUSE_SUPERVISOR_ECALL 0xa
|
2018-12-11 21:54:06 +08:00
|
|
|
#define CAUSE_MACHINE_ECALL 0xb
|
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|
|
#define CAUSE_FETCH_PAGE_FAULT 0xc
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|
|
#define CAUSE_LOAD_PAGE_FAULT 0xd
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|
|
#define CAUSE_STORE_PAGE_FAULT 0xf
|
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|
|
|
2018-12-24 19:15:00 +08:00
|
|
|
#define INSN_MATCH_LB 0x3
|
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|
|
#define INSN_MASK_LB 0x707f
|
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|
|
#define INSN_MATCH_LH 0x1003
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|
|
#define INSN_MASK_LH 0x707f
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|
|
#define INSN_MATCH_LW 0x2003
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|
|
#define INSN_MASK_LW 0x707f
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|
|
#define INSN_MATCH_LD 0x3003
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|
|
#define INSN_MASK_LD 0x707f
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|
#define INSN_MATCH_LBU 0x4003
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|
|
#define INSN_MASK_LBU 0x707f
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|
|
#define INSN_MATCH_LHU 0x5003
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|
|
#define INSN_MASK_LHU 0x707f
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|
|
#define INSN_MATCH_LWU 0x6003
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|
|
#define INSN_MASK_LWU 0x707f
|
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|
|
#define INSN_MATCH_SB 0x23
|
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|
|
#define INSN_MASK_SB 0x707f
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|
|
#define INSN_MATCH_SH 0x1023
|
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|
|
#define INSN_MASK_SH 0x707f
|
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|
|
#define INSN_MATCH_SW 0x2023
|
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|
|
#define INSN_MASK_SW 0x707f
|
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|
#define INSN_MATCH_SD 0x3023
|
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|
|
#define INSN_MASK_SD 0x707f
|
|
|
|
|
2019-01-03 13:07:43 +08:00
|
|
|
#define INSN_MATCH_FLW 0x2007
|
|
|
|
#define INSN_MASK_FLW 0x707f
|
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|
|
#define INSN_MATCH_FLD 0x3007
|
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|
|
#define INSN_MASK_FLD 0x707f
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|
|
#define INSN_MATCH_FLQ 0x4007
|
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|
|
#define INSN_MASK_FLQ 0x707f
|
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|
|
#define INSN_MATCH_FSW 0x2027
|
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|
|
#define INSN_MASK_FSW 0x707f
|
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|
|
#define INSN_MATCH_FSD 0x3027
|
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|
|
#define INSN_MASK_FSD 0x707f
|
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|
|
#define INSN_MATCH_FSQ 0x4027
|
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|
|
#define INSN_MASK_FSQ 0x707f
|
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|
|
|
2018-12-24 19:15:00 +08:00
|
|
|
#define INSN_MATCH_C_LD 0x6000
|
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|
|
#define INSN_MASK_C_LD 0xe003
|
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|
|
#define INSN_MATCH_C_SD 0xe000
|
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|
|
#define INSN_MASK_C_SD 0xe003
|
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|
|
#define INSN_MATCH_C_LW 0x4000
|
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|
|
#define INSN_MASK_C_LW 0xe003
|
|
|
|
#define INSN_MATCH_C_SW 0xc000
|
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|
|
#define INSN_MASK_C_SW 0xe003
|
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|
|
#define INSN_MATCH_C_LDSP 0x6002
|
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|
|
#define INSN_MASK_C_LDSP 0xe003
|
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|
|
#define INSN_MATCH_C_SDSP 0xe002
|
|
|
|
#define INSN_MASK_C_SDSP 0xe003
|
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|
|
#define INSN_MATCH_C_LWSP 0x4002
|
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|
|
#define INSN_MASK_C_LWSP 0xe003
|
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|
|
#define INSN_MATCH_C_SWSP 0xc002
|
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|
|
#define INSN_MASK_C_SWSP 0xe003
|
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|
|
#define INSN_MATCH_C_FLD 0x2000
|
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|
|
#define INSN_MASK_C_FLD 0xe003
|
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|
|
#define INSN_MATCH_C_FLW 0x6000
|
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|
|
#define INSN_MASK_C_FLW 0xe003
|
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|
|
#define INSN_MATCH_C_FSD 0xa000
|
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|
|
#define INSN_MASK_C_FSD 0xe003
|
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|
|
#define INSN_MATCH_C_FSW 0xe000
|
|
|
|
#define INSN_MASK_C_FSW 0xe003
|
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|
|
#define INSN_MATCH_C_FLDSP 0x2002
|
|
|
|
#define INSN_MASK_C_FLDSP 0xe003
|
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|
|
#define INSN_MATCH_C_FSDSP 0xa002
|
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|
|
#define INSN_MASK_C_FSDSP 0xe003
|
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|
|
#define INSN_MATCH_C_FLWSP 0x6002
|
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|
|
#define INSN_MASK_C_FLWSP 0xe003
|
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|
|
#define INSN_MATCH_C_FSWSP 0xe002
|
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|
|
#define INSN_MASK_C_FSWSP 0xe003
|
|
|
|
|
2019-04-05 20:47:11 +08:00
|
|
|
#define INSN_MASK_WFI 0xffffff00
|
|
|
|
#define INSN_MATCH_WFI 0x10500000
|
|
|
|
|
2018-12-24 19:15:00 +08:00
|
|
|
#define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4)
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|
|
|
|
|
|
#if __riscv_xlen == 64
|
|
|
|
#define LOG_REGBYTES 3
|
|
|
|
#else
|
|
|
|
#define LOG_REGBYTES 2
|
|
|
|
#endif
|
|
|
|
#define REGBYTES (1 << LOG_REGBYTES)
|
|
|
|
|
|
|
|
#define SH_RD 7
|
|
|
|
#define SH_RS1 15
|
|
|
|
#define SH_RS2 20
|
|
|
|
#define SH_RS2C 2
|
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|
|
|
|
|
|
#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
|
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|
|
#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
|
|
|
|
(RV_X(x, 10, 3) << 3) | \
|
|
|
|
(RV_X(x, 5, 1) << 6))
|
|
|
|
#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
|
|
|
|
(RV_X(x, 5, 2) << 6))
|
|
|
|
#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
|
|
|
|
(RV_X(x, 12, 1) << 5) | \
|
|
|
|
(RV_X(x, 2, 2) << 6))
|
|
|
|
#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
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|
|
|
(RV_X(x, 12, 1) << 5) | \
|
|
|
|
(RV_X(x, 2, 3) << 6))
|
|
|
|
#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
|
|
|
|
(RV_X(x, 7, 2) << 6))
|
|
|
|
#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
|
|
|
|
(RV_X(x, 7, 3) << 6))
|
|
|
|
#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
|
|
|
|
#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
|
|
|
|
#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
|
|
|
|
|
|
|
|
#define SHIFT_RIGHT(x, y) \
|
|
|
|
((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
|
|
|
|
|
|
|
|
#define REG_MASK \
|
|
|
|
((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
|
|
|
|
|
|
|
|
#define REG_OFFSET(insn, pos) \
|
|
|
|
(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
|
|
|
|
|
|
|
|
#define REG_PTR(insn, pos, regs) \
|
|
|
|
(ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
|
|
|
|
|
|
|
|
#define GET_RM(insn) (((insn) >> 12) & 7)
|
|
|
|
|
|
|
|
#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
|
|
|
|
#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
|
|
|
|
#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
|
|
|
|
#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
|
|
|
|
#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
|
|
|
|
#define GET_SP(regs) (*REG_PTR(2, 0, regs))
|
|
|
|
#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
|
|
|
|
#define IMM_I(insn) ((s32)(insn) >> 20)
|
|
|
|
#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
|
|
|
|
(s32)(((insn) >> 7) & 0x1f))
|
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#define MASK_FUNCT3 0x7000
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2019-04-11 08:41:46 +08:00
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/* clang-format on */
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2018-12-11 21:54:06 +08:00
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#endif
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