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opensbi/lib/sbi/riscv_asm.c

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Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
/*
all: Update copyright header in all files This patch updates copyright header in all files as follows: 1. Makes "SPDX-License-Identifier: BSD-2-Clause" as first line 2. Change copyright year to 2019 for Western Digital Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-01-24 14:11:10 +08:00
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
*
* Authors:
* Anup Patel <anup.patel@wdc.com>
*/
#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_error.h>
lib: Fix CPU capabilities detection function On some platforms, misa may not be implemented. On such a platform, reading misa will get 0. At this time, platform is required to implement a non-standard function to detect the CPU's capabilities. Therefore, this modification add interfaces for non-standard function. The MXL field of misa is always at the highest two bits, whether it is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification fixes the use of a fixed offset to detect the machine length. Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-11-26 18:36:29 +08:00
#include <sbi/sbi_platform.h>
lib: sbi: Add BUG() macro for csr_read/write_num() and misa_string() We use BUG() macro in csr_read_num(), csr_write_num(), and misa_string() functions for unhandled cases. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2021-09-16 12:32:50 +08:00
#include <sbi/sbi_console.h>
lib: Fix CPU capabilities detection function On some platforms, misa may not be implemented. On such a platform, reading misa will get 0. At this time, platform is required to implement a non-standard function to detect the CPU's capabilities. Therefore, this modification add interfaces for non-standard function. The MXL field of misa is always at the highest two bits, whether it is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification fixes the use of a fixed offset to detect the machine length. Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-11-26 18:36:29 +08:00
lib: Add error detection for misa_extension Add assertions for misa_extension to prevent incoming illegal characters. Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-11-27 14:16:52 +08:00
/* determine CPU extension, return non-zero support */
int misa_extension_imp(char ext)
lib: Fix CPU capabilities detection function On some platforms, misa may not be implemented. On such a platform, reading misa will get 0. At this time, platform is required to implement a non-standard function to detect the CPU's capabilities. Therefore, this modification add interfaces for non-standard function. The MXL field of misa is always at the highest two bits, whether it is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification fixes the use of a fixed offset to detect the machine length. Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-11-26 18:36:29 +08:00
{
unsigned long misa = csr_read(CSR_MISA);
lib: sbi: Improve misa_string() implementation The RISC-V ISA string does not follow alphabetical order. Instead, we have a RISC-V specific ordering of extensions in the RISC-V ISA string. This patch improves misa_string() implementation to return a valid RISC-V ISA string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-05 14:16:25 +08:00
if (misa) {
if ('A' <= ext && ext <= 'Z')
return misa & (1 << (ext - 'A'));
if ('a' <= ext && ext <= 'z')
return misa & (1 << (ext - 'a'));
return 0;
}
lib: Fix CPU capabilities detection function On some platforms, misa may not be implemented. On such a platform, reading misa will get 0. At this time, platform is required to implement a non-standard function to detect the CPU's capabilities. Therefore, this modification add interfaces for non-standard function. The MXL field of misa is always at the highest two bits, whether it is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification fixes the use of a fixed offset to detect the machine length. Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-11-26 18:36:29 +08:00
return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext);
}
int misa_xlen(void)
{
long r;
if (csr_read(CSR_MISA) == 0)
return sbi_platform_misa_xlen(sbi_platform_thishart_ptr());
__asm__ __volatile__(
"csrr t0, misa\n\t"
"slti t1, t0, 0\n\t"
"slli t1, t1, 1\n\t"
"slli t0, t0, 1\n\t"
"slti t0, t0, 0\n\t"
"add %0, t0, t1"
: "=r"(r)
:
: "t0", "t1");
return r ? r : -1;
}
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
lib: sbi: Improve misa_string() implementation The RISC-V ISA string does not follow alphabetical order. Instead, we have a RISC-V specific ordering of extensions in the RISC-V ISA string. This patch improves misa_string() implementation to return a valid RISC-V ISA string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-05 14:16:25 +08:00
void misa_string(int xlen, char *out, unsigned int out_sz)
{
unsigned int i, pos = 0;
const char valid_isa_order[] = "iemafdqclbjtpvnsuhkorwxyzg";
if (!out)
return;
if (5 <= (out_sz - pos)) {
out[pos++] = 'r';
out[pos++] = 'v';
switch (xlen) {
case 1:
out[pos++] = '3';
out[pos++] = '2';
break;
case 2:
out[pos++] = '6';
out[pos++] = '4';
break;
case 3:
out[pos++] = '1';
out[pos++] = '2';
out[pos++] = '8';
break;
default:
lib: sbi: Improve fatal error handling BUG and BUG_ON are not informative and are rather lazy interfaces, only telling the user that something went wrong in a given function, but not what, requiring the user to find the sources corresponding to their firmware (which may not be available) and figure out how that BUG(_ON) was hit. Even SBI_ASSERT in its current form, which does include the condition that triggered it in the output, isn't necessarily very informative. In some cases, the error may be fixable by the user, but they need to know the problem in order to have any hope of fixing it. It's also a nuisance for developers, whose development trees may have changed significantly since the release in question being used, and so line numbers can make it harder for them to understand which error case a user has hit. This patch introduces a new sbi_panic function which is printf-like, allowing detailed error messages to be printed to the console. BUG and BUG_ON are removed, since the former is just a worse form of sbi_panic and the latter is a worse version of SBI_ASSERT. Finally, SBI_ASSERT is augmented to take a set of arguments to pass to sbi_panic on failure, used like so (sbi_boot_print_hart's current error case, which currently manually calls sbi_printf and sbi_hart_hang): SBI_ASSERT(xlen >= 1, ("Error %d getting MISA XLEN\n", xlen)); The existing users of BUG are replaced with calls to sbi_panic along with informative error messages. BUG_ON and SBI_ASSERT were unused (and, in the case of SBI_ASSERT, remain unused). Many existing users of sbi_hart_hang should be converted to use either sbi_panic or SBI_ASSERT after this commit. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2021-11-22 01:30:22 +08:00
sbi_panic("%s: Unknown misa.MXL encoding %d",
__func__, xlen);
lib: sbi: Improve misa_string() implementation The RISC-V ISA string does not follow alphabetical order. Instead, we have a RISC-V specific ordering of extensions in the RISC-V ISA string. This patch improves misa_string() implementation to return a valid RISC-V ISA string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-05 14:16:25 +08:00
return;
}
}
for (i = 0; i < array_size(valid_isa_order) && (pos < out_sz); i++) {
if (misa_extension_imp(valid_isa_order[i]))
out[pos++] = valid_isa_order[i];
}
if (pos < out_sz)
out[pos++] = '\0';
}
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
unsigned long csr_read_num(int csr_num)
{
lib: sbi: Improve PMP CSR detection and progamming As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-08-18 15:58:08 +08:00
#define switchcase_csr_read(__csr_num, __val) \
case __csr_num: \
__val = csr_read(__csr_num); \
break;
#define switchcase_csr_read_2(__csr_num, __val) \
switchcase_csr_read(__csr_num + 0, __val) \
switchcase_csr_read(__csr_num + 1, __val)
#define switchcase_csr_read_4(__csr_num, __val) \
switchcase_csr_read_2(__csr_num + 0, __val) \
switchcase_csr_read_2(__csr_num + 2, __val)
#define switchcase_csr_read_8(__csr_num, __val) \
switchcase_csr_read_4(__csr_num + 0, __val) \
switchcase_csr_read_4(__csr_num + 4, __val)
#define switchcase_csr_read_16(__csr_num, __val) \
switchcase_csr_read_8(__csr_num + 0, __val) \
switchcase_csr_read_8(__csr_num + 8, __val)
#define switchcase_csr_read_32(__csr_num, __val) \
switchcase_csr_read_16(__csr_num + 0, __val) \
switchcase_csr_read_16(__csr_num + 16, __val)
#define switchcase_csr_read_64(__csr_num, __val) \
switchcase_csr_read_32(__csr_num + 0, __val) \
switchcase_csr_read_32(__csr_num + 32, __val)
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
unsigned long ret = 0;
switch (csr_num) {
lib: sbi: Improve PMP CSR detection and progamming As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-08-18 15:58:08 +08:00
switchcase_csr_read_16(CSR_PMPCFG0, ret)
switchcase_csr_read_64(CSR_PMPADDR0, ret)
lib: sbi: Use csr_read/write_num to read/update PMU counters Currently, csr_read/write_num functions are used to read/write PMP related CSRs where CSR value is decided at runtime. Expand this function to include PMU related CSRs as well. Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Xiang W <wxjstz@126.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-07-11 00:18:09 +08:00
switchcase_csr_read(CSR_MCYCLE, ret)
switchcase_csr_read(CSR_MINSTRET, ret)
switchcase_csr_read(CSR_MHPMCOUNTER3, ret)
switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret)
switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret)
switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret)
lib: sbi: Update csr_read/write_num for PMU The Sscofpmf extension introduces mhpmevent[h] csrs to handle filtering /overflow bits in RV32. There is no way to read/write mcountinhibit using mcountinhibit csr using a variable. Updated the support to read/write mhpmevent[h] and mcountinhibit csr. Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-11-09 02:52:57 +08:00
switchcase_csr_read(CSR_MCOUNTINHIBIT, ret)
switchcase_csr_read(CSR_MHPMEVENT3, ret)
switchcase_csr_read_4(CSR_MHPMEVENT4, ret)
switchcase_csr_read_8(CSR_MHPMEVENT8, ret)
switchcase_csr_read_16(CSR_MHPMEVENT16, ret)
lib: sbi: Use csr_read/write_num to read/update PMU counters Currently, csr_read/write_num functions are used to read/write PMP related CSRs where CSR value is decided at runtime. Expand this function to include PMU related CSRs as well. Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Xiang W <wxjstz@126.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-07-11 00:18:09 +08:00
#if __riscv_xlen == 32
switchcase_csr_read(CSR_MCYCLEH, ret)
switchcase_csr_read(CSR_MINSTRETH, ret)
switchcase_csr_read(CSR_MHPMCOUNTER3H, ret)
switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret)
switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret)
switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret)
lib: sbi: Update csr_read/write_num for PMU The Sscofpmf extension introduces mhpmevent[h] csrs to handle filtering /overflow bits in RV32. There is no way to read/write mcountinhibit using mcountinhibit csr using a variable. Updated the support to read/write mhpmevent[h] and mcountinhibit csr. Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-11-09 02:52:57 +08:00
switchcase_csr_read(CSR_MHPMEVENT3H, ret)
switchcase_csr_read_4(CSR_MHPMEVENT4H, ret)
switchcase_csr_read_8(CSR_MHPMEVENT8H, ret)
switchcase_csr_read_16(CSR_MHPMEVENT16H, ret)
lib: sbi: Use csr_read/write_num to read/update PMU counters Currently, csr_read/write_num functions are used to read/write PMP related CSRs where CSR value is decided at runtime. Expand this function to include PMU related CSRs as well. Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Xiang W <wxjstz@126.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-07-11 00:18:09 +08:00
#endif
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
default:
lib: sbi: Improve fatal error handling BUG and BUG_ON are not informative and are rather lazy interfaces, only telling the user that something went wrong in a given function, but not what, requiring the user to find the sources corresponding to their firmware (which may not be available) and figure out how that BUG(_ON) was hit. Even SBI_ASSERT in its current form, which does include the condition that triggered it in the output, isn't necessarily very informative. In some cases, the error may be fixable by the user, but they need to know the problem in order to have any hope of fixing it. It's also a nuisance for developers, whose development trees may have changed significantly since the release in question being used, and so line numbers can make it harder for them to understand which error case a user has hit. This patch introduces a new sbi_panic function which is printf-like, allowing detailed error messages to be printed to the console. BUG and BUG_ON are removed, since the former is just a worse form of sbi_panic and the latter is a worse version of SBI_ASSERT. Finally, SBI_ASSERT is augmented to take a set of arguments to pass to sbi_panic on failure, used like so (sbi_boot_print_hart's current error case, which currently manually calls sbi_printf and sbi_hart_hang): SBI_ASSERT(xlen >= 1, ("Error %d getting MISA XLEN\n", xlen)); The existing users of BUG are replaced with calls to sbi_panic along with informative error messages. BUG_ON and SBI_ASSERT were unused (and, in the case of SBI_ASSERT, remain unused). Many existing users of sbi_hart_hang should be converted to use either sbi_panic or SBI_ASSERT after this commit. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2021-11-22 01:30:22 +08:00
sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
break;
};
return ret;
lib: sbi: Improve PMP CSR detection and progamming As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-08-18 15:58:08 +08:00
#undef switchcase_csr_read_64
#undef switchcase_csr_read_32
#undef switchcase_csr_read_16
#undef switchcase_csr_read_8
#undef switchcase_csr_read_4
#undef switchcase_csr_read_2
#undef switchcase_csr_read
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
}
void csr_write_num(int csr_num, unsigned long val)
{
lib: sbi: Improve PMP CSR detection and progamming As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-08-18 15:58:08 +08:00
#define switchcase_csr_write(__csr_num, __val) \
case __csr_num: \
csr_write(__csr_num, __val); \
break;
#define switchcase_csr_write_2(__csr_num, __val) \
switchcase_csr_write(__csr_num + 0, __val) \
switchcase_csr_write(__csr_num + 1, __val)
#define switchcase_csr_write_4(__csr_num, __val) \
switchcase_csr_write_2(__csr_num + 0, __val) \
switchcase_csr_write_2(__csr_num + 2, __val)
#define switchcase_csr_write_8(__csr_num, __val) \
switchcase_csr_write_4(__csr_num + 0, __val) \
switchcase_csr_write_4(__csr_num + 4, __val)
#define switchcase_csr_write_16(__csr_num, __val) \
switchcase_csr_write_8(__csr_num + 0, __val) \
switchcase_csr_write_8(__csr_num + 8, __val)
#define switchcase_csr_write_32(__csr_num, __val) \
switchcase_csr_write_16(__csr_num + 0, __val) \
switchcase_csr_write_16(__csr_num + 16, __val)
#define switchcase_csr_write_64(__csr_num, __val) \
switchcase_csr_write_32(__csr_num + 0, __val) \
switchcase_csr_write_32(__csr_num + 32, __val)
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
switch (csr_num) {
lib: sbi: Improve PMP CSR detection and progamming As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-08-18 15:58:08 +08:00
switchcase_csr_write_16(CSR_PMPCFG0, val)
switchcase_csr_write_64(CSR_PMPADDR0, val)
lib: sbi: Use csr_read/write_num to read/update PMU counters Currently, csr_read/write_num functions are used to read/write PMP related CSRs where CSR value is decided at runtime. Expand this function to include PMU related CSRs as well. Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Xiang W <wxjstz@126.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-07-11 00:18:09 +08:00
switchcase_csr_write(CSR_MCYCLE, val)
switchcase_csr_write(CSR_MINSTRET, val)
switchcase_csr_write(CSR_MHPMCOUNTER3, val)
switchcase_csr_write_4(CSR_MHPMCOUNTER4, val)
switchcase_csr_write_8(CSR_MHPMCOUNTER8, val)
switchcase_csr_write_16(CSR_MHPMCOUNTER16, val)
#if __riscv_xlen == 32
switchcase_csr_write(CSR_MCYCLEH, val)
switchcase_csr_write(CSR_MINSTRETH, val)
switchcase_csr_write(CSR_MHPMCOUNTER3H, val)
switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val)
switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val)
switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val)
lib: sbi: Update csr_read/write_num for PMU The Sscofpmf extension introduces mhpmevent[h] csrs to handle filtering /overflow bits in RV32. There is no way to read/write mcountinhibit using mcountinhibit csr using a variable. Updated the support to read/write mhpmevent[h] and mcountinhibit csr. Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-11-09 02:52:57 +08:00
switchcase_csr_write(CSR_MHPMEVENT3H, val)
switchcase_csr_write_4(CSR_MHPMEVENT4H, val)
switchcase_csr_write_8(CSR_MHPMEVENT8H, val)
switchcase_csr_write_16(CSR_MHPMEVENT16H, val)
lib: sbi: Use csr_read/write_num to read/update PMU counters Currently, csr_read/write_num functions are used to read/write PMP related CSRs where CSR value is decided at runtime. Expand this function to include PMU related CSRs as well. Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Xiang W <wxjstz@126.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-07-11 00:18:09 +08:00
#endif
switchcase_csr_write(CSR_MCOUNTINHIBIT, val)
switchcase_csr_write(CSR_MHPMEVENT3, val)
switchcase_csr_write_4(CSR_MHPMEVENT4, val)
switchcase_csr_write_8(CSR_MHPMEVENT8, val)
switchcase_csr_write_16(CSR_MHPMEVENT16, val)
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
default:
lib: sbi: Improve fatal error handling BUG and BUG_ON are not informative and are rather lazy interfaces, only telling the user that something went wrong in a given function, but not what, requiring the user to find the sources corresponding to their firmware (which may not be available) and figure out how that BUG(_ON) was hit. Even SBI_ASSERT in its current form, which does include the condition that triggered it in the output, isn't necessarily very informative. In some cases, the error may be fixable by the user, but they need to know the problem in order to have any hope of fixing it. It's also a nuisance for developers, whose development trees may have changed significantly since the release in question being used, and so line numbers can make it harder for them to understand which error case a user has hit. This patch introduces a new sbi_panic function which is printf-like, allowing detailed error messages to be printed to the console. BUG and BUG_ON are removed, since the former is just a worse form of sbi_panic and the latter is a worse version of SBI_ASSERT. Finally, SBI_ASSERT is augmented to take a set of arguments to pass to sbi_panic on failure, used like so (sbi_boot_print_hart's current error case, which currently manually calls sbi_printf and sbi_hart_hang): SBI_ASSERT(xlen >= 1, ("Error %d getting MISA XLEN\n", xlen)); The existing users of BUG are replaced with calls to sbi_panic along with informative error messages. BUG_ON and SBI_ASSERT were unused (and, in the case of SBI_ASSERT, remain unused). Many existing users of sbi_hart_hang should be converted to use either sbi_panic or SBI_ASSERT after this commit. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2021-11-22 01:30:22 +08:00
sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
break;
};
lib: sbi: Improve PMP CSR detection and progamming As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-08-18 15:58:08 +08:00
#undef switchcase_csr_write_64
#undef switchcase_csr_write_32
#undef switchcase_csr_write_16
#undef switchcase_csr_write_8
#undef switchcase_csr_write_4
#undef switchcase_csr_write_2
#undef switchcase_csr_write
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
}
Revert "lib: Use __builtin_ctzl() in pmp_get()" This reverts commit 897b8fbdd92fcfad194417d348b8dad16ab0e17a. We are seeing compile errors using newlib based GCC cross-toolchain so we restore back old ctz() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-02-18 11:56:33 +08:00
static unsigned long ctz(unsigned long x)
{
unsigned long ret = 0;
lib: sbi: fix ctz bug The original version of ctz will cause an endless loop, if the parameter passed in is 0. This commit fixes this bug. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2021-09-15 14:50:52 +08:00
if (x == 0)
return 8 * sizeof(x);
Revert "lib: Use __builtin_ctzl() in pmp_get()" This reverts commit 897b8fbdd92fcfad194417d348b8dad16ab0e17a. We are seeing compile errors using newlib based GCC cross-toolchain so we restore back old ctz() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-02-18 11:56:33 +08:00
while (!(x & 1UL)) {
ret++;
x = x >> 1;
}
return ret;
}
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
unsigned long log2len)
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
{
int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
unsigned long cfgmask, pmpcfg;
unsigned long addrmask, pmpaddr;
/* check parameters */
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
if (n >= PMP_COUNT || log2len > __riscv_xlen || log2len < PMP_SHIFT)
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
return SBI_EINVAL;
lib: sbi: Fix coding style issues This fixes various coding style issues found in the SBI codes. No functional changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-09 11:52:41 +08:00
/* calculate PMP register and offset */
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
#if __riscv_xlen == 32
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
pmpcfg_shift = (n & 3) << 3;
#elif __riscv_xlen == 64
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
pmpcfg_shift = (n & 7) << 3;
#else
lib: pmp_set/pmp_get moved errors from runtime to compile time pmp_set/pmp_get calculates the location of the CSR register separately through conditional compilation. In the case of non-32-bit and 64-bit, we can report an error directly through #error without putting it at runtime Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-03-16 00:22:38 +08:00
# error "Unexpected __riscv_xlen"
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
#endif
pmpaddr_csr = CSR_PMPADDR0 + n;
/* encode PMP config */
lib: sbi: clear pmpcfg.A before setting in pmp_set() We should clear A bits in prot variable before enabling A_NA4 or A_NAPOT. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2021-11-08 17:43:03 +08:00
prot &= ~PMP_A;
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
prot |= (log2len == PMP_SHIFT) ? PMP_A_NA4 : PMP_A_NAPOT;
lib: sbi: Fix 32/64 bits variable compatibility On RV64,"unsigned long" is 64bit and "unsigned int" is 32bit. So in function "pmp_get" and "pmp_set", if "pmpcfg_shift >= 32", "0xff << pmpcfg_shift" will go beyond "unsigned int" width. This patch tries to fix this issue. In function 'pmp_get': cfgmask = (0xff << pmpcfg_shift); --> cfgmask = (0xffUL << pmpcfg_shift); In function 'pmp_set': cfgmask = ~(0xff << pmpcfg_shift); --> cfgmask = ~(0xffUL << pmpcfg_shift); Signed-off-by: Liush <liush.damon@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-06-19 11:55:19 +08:00
cfgmask = ~(0xffUL << pmpcfg_shift);
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask);
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
pmpcfg |= ((prot << pmpcfg_shift) & ~cfgmask);
/* encode PMP address */
if (log2len == PMP_SHIFT) {
pmpaddr = (addr >> PMP_SHIFT);
} else {
if (log2len == __riscv_xlen) {
pmpaddr = -1UL;
} else {
addrmask = (1UL << (log2len - PMP_SHIFT)) - 1;
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
pmpaddr = ((addr >> PMP_SHIFT) & ~addrmask);
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
pmpaddr |= (addrmask >> 1);
}
}
/* write csrs */
csr_write_num(pmpaddr_csr, pmpaddr);
csr_write_num(pmpcfg_csr, pmpcfg);
return 0;
}
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-07 18:20:33 +08:00
unsigned long *log2len)
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
{
int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
unsigned long cfgmask, pmpcfg, prot;
lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-07 18:20:33 +08:00
unsigned long t1, addr, len;
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
/* check parameters */
lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-07 18:20:33 +08:00
if (n >= PMP_COUNT || !prot_out || !addr_out || !log2len)
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
return SBI_EINVAL;
lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-07 18:20:33 +08:00
*prot_out = *addr_out = *log2len = 0;
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
/* calculate PMP register and offset */
#if __riscv_xlen == 32
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
pmpcfg_shift = (n & 3) << 3;
#elif __riscv_xlen == 64
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
pmpcfg_shift = (n & 7) << 3;
#else
lib: pmp_set/pmp_get moved errors from runtime to compile time pmp_set/pmp_get calculates the location of the CSR register separately through conditional compilation. In the case of non-32-bit and 64-bit, we can report an error directly through #error without putting it at runtime Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-03-16 00:22:38 +08:00
# error "Unexpected __riscv_xlen"
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
#endif
pmpaddr_csr = CSR_PMPADDR0 + n;
/* decode PMP config */
lib: sbi: Fix 32/64 bits variable compatibility On RV64,"unsigned long" is 64bit and "unsigned int" is 32bit. So in function "pmp_get" and "pmp_set", if "pmpcfg_shift >= 32", "0xff << pmpcfg_shift" will go beyond "unsigned int" width. This patch tries to fix this issue. In function 'pmp_get': cfgmask = (0xff << pmpcfg_shift); --> cfgmask = (0xffUL << pmpcfg_shift); In function 'pmp_set': cfgmask = ~(0xff << pmpcfg_shift); --> cfgmask = ~(0xffUL << pmpcfg_shift); Signed-off-by: Liush <liush.damon@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-06-19 11:55:19 +08:00
cfgmask = (0xffUL << pmpcfg_shift);
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
pmpcfg = csr_read_num(pmpcfg_csr) & cfgmask;
prot = pmpcfg >> pmpcfg_shift;
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
/* decode PMP address */
if ((prot & PMP_A) == PMP_A_NAPOT) {
addr = csr_read_num(pmpaddr_csr);
if (addr == -1UL) {
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
addr = 0;
lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-07 18:20:33 +08:00
len = __riscv_xlen;
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
} else {
Revert "lib: Use __builtin_ctzl() in pmp_get()" This reverts commit 897b8fbdd92fcfad194417d348b8dad16ab0e17a. We are seeing compile errors using newlib based GCC cross-toolchain so we restore back old ctz() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-02-18 11:56:33 +08:00
t1 = ctz(~addr);
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
addr = (addr & ~((1UL << t1) - 1)) << PMP_SHIFT;
lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-07 18:20:33 +08:00
len = (t1 + PMP_SHIFT + 1);
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
}
} else {
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
addr = csr_read_num(pmpaddr_csr) << PMP_SHIFT;
lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-07 18:20:33 +08:00
len = PMP_SHIFT;
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
}
/* return details */
all: run clang-format and update checked-in files Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-11 08:41:52 +08:00
*prot_out = prot;
*addr_out = addr;
lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API We extend sbi_hart_pmp_check_addr() API so that users can specify privilege mode of the address for checking PMP access permissions. To achieve this, we end-up converting "unsigned long *size" parameter to "unsigned long *log2len" for pmp_get() implementation so that we can deal with regions of "1UL << __riscv_xlen" size in a special case in sbi_hart_pmp_check_addr() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-07 18:20:33 +08:00
*log2len = len;
Initial commit. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11 21:54:06 +08:00
return 0;
}