lib: sbi: Refactor the code for enable extensions in menvfg CSR
Use 1 variable to store the value of menvcfg. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
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@ -207,13 +207,8 @@
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#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
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#if __riscv_xlen > 32
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#define ENVCFG_STCE (_ULL(1) << 63)
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#define ENVCFG_PBMTE (_ULL(1) << 62)
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#else
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#define ENVCFGH_STCE (_UL(1) << 31)
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#define ENVCFGH_PBMTE (_UL(1) << 30)
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#endif
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#define ENVCFG_CBZE (_UL(1) << 7)
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#define ENVCFG_CBCFE (_UL(1) << 6)
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#define ENVCFG_CBIE_SHIFT 4
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@ -33,11 +33,11 @@ static unsigned long hart_features_offset;
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static void mstatus_init(struct sbi_scratch *scratch)
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{
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unsigned long menvcfg_val, mstatus_val = 0;
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int cidx;
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unsigned long mstatus_val = 0;
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unsigned int mhpm_mask = sbi_hart_mhpm_mask(scratch);
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uint64_t mhpmevent_init_val = 0;
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uint64_t mstateen_val;
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uint64_t menvcfg_val, mstateen_val;
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/* Enable FPU */
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if (misa_extension('D') || misa_extension('F'))
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@ -108,6 +108,9 @@ static void mstatus_init(struct sbi_scratch *scratch)
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if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_12) {
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menvcfg_val = csr_read(CSR_MENVCFG);
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#if __riscv_xlen == 32
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menvcfg_val |= ((uint64_t)csr_read(CSR_MENVCFGH)) << 32;
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#endif
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/*
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* Set menvcfg.CBZE == 1
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@ -148,18 +151,13 @@ static void mstatus_init(struct sbi_scratch *scratch)
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* Enable access to stimecmp if sstc extension is present in the
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* hardware.
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*/
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSTC)) {
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#if __riscv_xlen == 32
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unsigned long menvcfgh_val;
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menvcfgh_val = csr_read(CSR_MENVCFGH);
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menvcfgh_val |= ENVCFGH_STCE;
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csr_write(CSR_MENVCFGH, menvcfgh_val);
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#else
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSTC))
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menvcfg_val |= ENVCFG_STCE;
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#endif
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}
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csr_write(CSR_MENVCFG, menvcfg_val);
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#if __riscv_xlen == 32
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csr_write(CSR_MENVCFGH, menvcfg_val >> 32);
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#endif
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/* Enable S-mode access to seed CSR */
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_ZKR)) {
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