Virtualization
/
opensbi
mirror of https://gitlab.com/qemu-project/opensbi.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

platform: Add AE350 cache control SBIs 

This patch contains the following AE350 specific SBIs:

- get mcache_ctl status
- get mmisc_ctl status
- set mcache_ctl status
- set mmisc_ctl status
- I-cache operation
- D-cache operation
- enable/disable L1-I-cache prefetch
- enable/disable L1-D-cache prefetch
- enable/disable non-blocking load store
- enable/disable write-around

Signed-off-by: Nylon Chen <nylon7@andestech.com>
Reviewed-by: Anup Patel <Anup.Patel@wdc.com>
Reviewed-by: Atish Patra <Atish.Patra@wdc.com>
This commit is contained in:
Nylon Chen 2020-06-09 13:56:58 +08:00 committed by Anup Patel
parent 980290651f
commit 32f87e5a86
5 changed files with 186 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

89
platform/andes/ae350/cache.c Normal file
View File

@ -0,0 +1,89 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2020 Andes Technology Corporation
*
* Authors:
* Nylon Chen <nylon7@andestech.com>
*/
#include <sbi/riscv_asm.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_types.h>
#include "platform.h"
uintptr_t mcall_set_mcache_ctl(unsigned long input)
{
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_MASK);
csr_write(CSR_MCACHECTL, input);
return 0;
}
uintptr_t mcall_set_mmisc_ctl(unsigned long input)
{
csr_clear(CSR_MMISCCTL, V5_MMISC_CTL_MASK);
csr_write(CSR_MMISCCTL, input);
return 0;
}
uintptr_t mcall_icache_op(unsigned int enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
asm volatile("fence.i\n\t");
}
return 0;
}
uintptr_t mcall_dcache_op(unsigned int enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
csr_write(CSR_MCCTLCOMMAND, V5_UCCTL_L1D_WBINVAL_ALL);
}
return 0;
}
uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
}
return 0;
}
uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
}
return 0;
}
uintptr_t mcall_non_blocking_load_store(unsigned long enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
}
return 0;
}
uintptr_t mcall_write_around(unsigned long enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
}
return 0;
}

17
platform/andes/ae350/cache.h Normal file
View File

@ -0,0 +1,17 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2020 Andes Technology Corporation
*
* Authors:
* Nylon Chen <nylon7@andestech.com>
*/
uintptr_t mcall_set_mcache_ctl(unsigned long input);
uintptr_t mcall_set_mmisc_ctl(unsigned long input);
uintptr_t mcall_icache_op(unsigned int enable);
uintptr_t mcall_dcache_op(unsigned int enable);
uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable);
uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable);
uintptr_t mcall_non_blocking_load_store(unsigned long enable);
uintptr_t mcall_write_around(unsigned long enable);

2
platform/andes/ae350/objects.mk
View File

@ -8,4 +8,4 @@
# Nylon Chen <nylon7@andestech.com> # Nylon Chen <nylon7@andestech.com>
# #
platform-objs-y += platform.o plicsw.o plmt.o platform-objs-y += cache.o platform.o plicsw.o plmt.o

31
platform/andes/ae350/platform.c
View File

@ -19,6 +19,7 @@
#include "platform.h" #include "platform.h"
#include "plicsw.h" #include "plicsw.h"
#include "plmt.h" #include "plmt.h"
#include "cache.h"
static struct plic_data plic = { static struct plic_data plic = {
.addr = AE350_PLIC_ADDR, .addr = AE350_PLIC_ADDR,
@ -128,6 +129,36 @@ static int ae350_vendor_ext_provider(long extid, long funcid,
{ {
int ret = 0; int ret = 0;
switch (funcid) { switch (funcid) {
case SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS:
*out_value = csr_read(CSR_MCACHECTL);
break;
case SBI_EXT_ANDES_GET_MMISC_CTL_STATUS:
*out_value = csr_read(CSR_MMISCCTL);
break;
case SBI_EXT_ANDES_SET_MCACHE_CTL:
ret = mcall_set_mcache_ctl(args[0]);
break;
case SBI_EXT_ANDES_SET_MMISC_CTL:
ret = mcall_set_mmisc_ctl(args[0]);
break;
case SBI_EXT_ANDES_ICACHE_OP:
ret = mcall_icache_op(args[0]);
break;
case SBI_EXT_ANDES_DCACHE_OP:
ret = mcall_dcache_op(args[0]);
break;
case SBI_EXT_ANDES_L1CACHE_I_PREFETCH:
ret = mcall_l1_cache_i_prefetch_op(args[0]);
break;
case SBI_EXT_ANDES_L1CACHE_D_PREFETCH:
ret = mcall_l1_cache_d_prefetch_op(args[0]);
break;
case SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE:
ret = mcall_non_blocking_load_store(args[0]);
break;
case SBI_EXT_ANDES_WRITE_AROUND:
ret = mcall_write_around(args[0]);
break;
default: default:
sbi_printf("Unsupported vendor sbi call : %ld\n", funcid); sbi_printf("Unsupported vendor sbi call : %ld\n", funcid);
asm volatile("ebreak"); asm volatile("ebreak");

48
platform/andes/ae350/platform.h
View File

@ -29,6 +29,19 @@
#define AE350_UART_REG_SHIFT 2 #define AE350_UART_REG_SHIFT 2
#define AE350_UART_REG_WIDTH 0 #define AE350_UART_REG_WIDTH 0
/*Memory and Miscellaneous Registers*/
#define CSR_MILMB 0x7c0
#define CSR_MDLMB 0x7c1
#define CSR_MECC_CDOE 0x7c2
#define CSR_MNVEC 0x7c3
#define CSR_MPFTCTL 0x7c5
#define CSR_MCACHECTL 0x7ca
#define CSR_MCCTLBEGINADDR 0x7cb
#define CSR_MCCTLCOMMAND 0x7cc
#define CSR_MCCTLDATA 0x7cc
#define CSR_SCCTLDATA 0x9cd
#define CSR_UCCTLBEGINADDR 0x80c
#define CSR_MMISCCTL 0x7d0
enum sbi_ext_andes_fid { enum sbi_ext_andes_fid {
SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0, SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0,
@ -43,6 +56,31 @@ enum sbi_ext_andes_fid {
SBI_EXT_ANDES_WRITE_AROUND, SBI_EXT_ANDES_WRITE_AROUND,
}; };
/* nds v5 mmisc_ctl register*/
#define V5_MMISC_CTL_VEC_PLIC_OFFSET 1
#define V5_MMISC_CTL_RVCOMPM_OFFSET 2
#define V5_MMISC_CTL_BRPE_OFFSET 3
#define V5_MMISC_CTL_MSA_OR_UNA_OFFSET 6
#define V5_MMISC_CTL_NON_BLOCKING_OFFSET 8
#define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET 9
#define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET 10
#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1 13
#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2 14
#define V5_MMISC_CTL_VEC_PLIC_EN (1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET)
#define V5_MMISC_CTL_RVCOMPM_EN (1UL << V5_MMISC_CTL_RVCOMPM_OFFSET)
#define V5_MMISC_CTL_BRPE_EN (1UL << V5_MMISC_CTL_BRPE_OFFSET)
#define V5_MMISC_CTL_MSA_OR_UNA_EN (1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET)
#define V5_MMISC_CTL_NON_BLOCKING_EN (1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET)
#define V5_MCACHE_CTL_L1I_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET)
#define V5_MCACHE_CTL_L1D_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET)
#define V5_MCACHE_CTL_DC_WAROUND_1_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1)
#define V5_MCACHE_CTL_DC_WAROUND_2_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2)
#define V5_MMISC_CTL_MASK (V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN \
| V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | V5_MMISC_CTL_NON_BLOCKING_EN)
/* nds mcache_ctl register*/
#define V5_MCACHE_CTL_IC_EN_OFFSET 0 #define V5_MCACHE_CTL_IC_EN_OFFSET 0
#define V5_MCACHE_CTL_DC_EN_OFFSET 1 #define V5_MCACHE_CTL_DC_EN_OFFSET 1
#define V5_MCACHE_CTL_IC_ECCEN_OFFSET 2 #define V5_MCACHE_CTL_IC_ECCEN_OFFSET 2
@ -51,12 +89,22 @@ enum sbi_ext_andes_fid {
#define V5_MCACHE_CTL_DC_RWECC_OFFSET 7 #define V5_MCACHE_CTL_DC_RWECC_OFFSET 7
#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8 #define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
/*nds cctl command*/
#define V5_UCCTL_L1D_WBINVAL_ALL 6
#define V5_UCCTL_L1D_WB_ALL 7
#define V5_MCACHE_CTL_IC_EN (1UL << V5_MCACHE_CTL_IC_EN_OFFSET) #define V5_MCACHE_CTL_IC_EN (1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
#define V5_MCACHE_CTL_DC_EN (1UL << V5_MCACHE_CTL_DC_EN_OFFSET) #define V5_MCACHE_CTL_DC_EN (1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
#define V5_MCACHE_CTL_IC_RWECC (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET) #define V5_MCACHE_CTL_IC_RWECC (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
#define V5_MCACHE_CTL_DC_RWECC (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET) #define V5_MCACHE_CTL_DC_RWECC (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
#define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET) #define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
#define V5_MCACHE_CTL_MASK (V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN \
| V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC \
| V5_MCACHE_CTL_CCTL_SUEN | V5_MCACHE_CTL_L1I_PREFETCH_EN \
| V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN \
| V5_MCACHE_CTL_DC_WAROUND_2_EN)
#define V5_L2C_CTL_OFFSET 0x8 #define V5_L2C_CTL_OFFSET 0x8
#define V5_L2C_CTL_ENABLE_OFFSET 0 #define V5_L2C_CTL_ENABLE_OFFSET 0
#define V5_L2C_CTL_IPFDPT_OFFSET 3 #define V5_L2C_CTL_IPFDPT_OFFSET 3