From 385b5afe7d5e8d5d552637973955155862de2a79 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Sun, 16 Dec 2018 10:05:39 +0530 Subject: [PATCH] plat: Add separate platform support for QEMU sifive_u machine The QEMU sifive_u machine is not excatly same as HiFive Unleashed board hence we add separate platform support for QEMU sifive_u machine. Signed-off-by: Anup Patel --- plat/qemu/sifive_u/config.mk | 31 +++++++++ plat/qemu/sifive_u/objects.mk | 10 +++ plat/qemu/sifive_u/platform.c | 114 ++++++++++++++++++++++++++++++++++ 3 files changed, 155 insertions(+) create mode 100644 plat/qemu/sifive_u/config.mk create mode 100644 plat/qemu/sifive_u/objects.mk create mode 100644 plat/qemu/sifive_u/platform.c diff --git a/plat/qemu/sifive_u/config.mk b/plat/qemu/sifive_u/config.mk new file mode 100644 index 0000000..ab5d52b --- /dev/null +++ b/plat/qemu/sifive_u/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (c) 2018 Western Digital Corporation or its affiliates. +# +# Authors: +# Anup Patel +# +# SPDX-License-Identifier: BSD-2-Clause +# + +# Essential defines required by SBI platform +plat-cppflags-y = -DPLAT_NAME="QEMU SiFive Unleashed" +plat-cppflags-y+= -DPLAT_HART_COUNT=1 +plat-cppflags-y+= -DPLAT_HART_STACK_SIZE=8192 +plat-cppflags-y+= -DPLAT_TEXT_START=0x80000000 + +# Compiler flags +plat-cflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany +plat-asflags-y =-mabi=lp64 -march=rv64imafdc -mcmodel=medany +plat-ldflags-y = + +# Common drivers to enable +PLAT_IRQCHIP_PLIC=y +PLAT_SERIAL_SIFIVE_UART=y +PLAT_SYS_CLINT=y + +# Blobs to build +FW_JUMP=y +FW_JUMP_ADDR=0x80200000 +FW_JUMP_FDT_OFFSET=0x2000000 +FW_PAYLOAD=y +FW_PAYLOAD_FDT_OFFSET=0x2000000 diff --git a/plat/qemu/sifive_u/objects.mk b/plat/qemu/sifive_u/objects.mk new file mode 100644 index 0000000..03ee2fe --- /dev/null +++ b/plat/qemu/sifive_u/objects.mk @@ -0,0 +1,10 @@ +# +# Copyright (c) 2018 Western Digital Corporation or its affiliates. +# +# Authors: +# Anup Patel +# +# SPDX-License-Identifier: BSD-2-Clause +# + +plat-objs-y += platform.o diff --git a/plat/qemu/sifive_u/platform.c b/plat/qemu/sifive_u/platform.c new file mode 100644 index 0000000..a4a401e --- /dev/null +++ b/plat/qemu/sifive_u/platform.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2018 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + * + * SPDX-License-Identifier: BSD-2-Clause + */ + +#include +#include +#include +#include +#include +#include + +#define SIFIVE_U_SYS_CLK 1000000000 +#define SIFIVE_U_PERIPH_CLK (SIFIVE_U_SYS_CLK / 2) + +#define SIFIVE_U_CLINT_ADDR 0x2000000 + +#define SIFIVE_U_PLIC_ADDR 0xc000000 +#define SIFIVE_U_PLIC_NUM_SOURCES 0x35 +#define SIFIVE_U_PLIC_NUM_PRIORITIES 7 + +#define SIFIVE_U_UART0_ADDR 0x10013000 +#define SIFIVE_U_UART1_ADDR 0x10023000 + +static int sifive_u_cold_final_init(void) +{ + return plic_fdt_fixup(sbi_scratch_thishart_arg1_ptr(), "riscv,plic0"); +} + +static u32 sifive_u_pmp_region_count(u32 target_hart) +{ + return 1; +} + +static int sifive_u_pmp_region_info(u32 target_hart, u32 index, + ulong *prot, ulong *addr, ulong *log2size) +{ + int ret = 0; + + switch (index) { + case 0: + *prot = PMP_R | PMP_W | PMP_X; + *addr = 0; + *log2size = __riscv_xlen; + break; + default: + ret = -1; + break; + }; + + return ret; +} + +static int sifive_u_console_init(void) +{ + return sifive_uart_init(SIFIVE_U_UART0_ADDR, + SIFIVE_U_PERIPH_CLK, 115200); +} + +static int sifive_u_cold_irqchip_init(void) +{ + return plic_cold_irqchip_init(SIFIVE_U_PLIC_ADDR, + SIFIVE_U_PLIC_NUM_SOURCES, + PLAT_HART_COUNT); +} + +static int sifive_u_cold_ipi_init(void) +{ + return clint_cold_ipi_init(SIFIVE_U_CLINT_ADDR, + PLAT_HART_COUNT); +} + +static int sifive_u_cold_timer_init(void) +{ + return clint_cold_timer_init(SIFIVE_U_CLINT_ADDR, + PLAT_HART_COUNT); +} + +static int sifive_u_system_down(u32 type) +{ + /* For now nothing to do. */ + return 0; +} + +struct sbi_platform platform = { + .name = STRINGIFY(PLAT_NAME), + .features = SBI_PLATFORM_HAS_MMIO_TIMER_VALUE, + .hart_count = PLAT_HART_COUNT, + .hart_stack_size = PLAT_HART_STACK_SIZE, + .pmp_region_count = sifive_u_pmp_region_count, + .pmp_region_info = sifive_u_pmp_region_info, + .cold_final_init = sifive_u_cold_final_init, + .console_putc = sifive_uart_putc, + .console_getc = sifive_uart_getc, + .console_init = sifive_u_console_init, + .cold_irqchip_init = sifive_u_cold_irqchip_init, + .warm_irqchip_init = plic_warm_irqchip_init, + .ipi_inject = clint_ipi_inject, + .ipi_sync = clint_ipi_sync, + .ipi_clear = clint_ipi_clear, + .warm_ipi_init = clint_warm_ipi_init, + .cold_ipi_init = sifive_u_cold_ipi_init, + .timer_value = clint_timer_value, + .timer_event_stop = clint_timer_event_stop, + .timer_event_start = clint_timer_event_start, + .warm_timer_init = clint_warm_timer_init, + .cold_timer_init = sifive_u_cold_timer_init, + .system_reboot = sifive_u_system_down, + .system_shutdown = sifive_u_system_down +};