platform: Remove the ipi_sync method from all platforms.
OpenSBI manages outstanding TLB flush requests by queueing them in a fifo synchronously. An ipi sync which uses an atomic operation on MMIO address is no longer required. Remove the ipi sync method from platform header and all usage. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
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@ -90,8 +90,6 @@ struct sbi_platform_operations {
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/** Send IPI to a target HART */
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void (*ipi_send)(u32 target_hart);
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/** Wait for target HART to acknowledge IPI */
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void (*ipi_sync)(u32 target_hart);
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/** Clear IPI for a target HART */
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void (*ipi_clear)(u32 target_hart);
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/** Initialize IPI for current HART */
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@ -370,19 +368,6 @@ static inline void sbi_platform_ipi_send(const struct sbi_platform *plat,
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sbi_platform_ops(plat)->ipi_send(target_hart);
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}
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/**
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* Wait for target HART to acknowledge IPI
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*
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* @param plat pointer to struct sbi_platform
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* @param target_hart HART ID of IPI target
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*/
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static inline void sbi_platform_ipi_sync(const struct sbi_platform *plat,
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u32 target_hart)
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{
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if (plat && sbi_platform_ops(plat)->ipi_sync)
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sbi_platform_ops(plat)->ipi_sync(target_hart);
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}
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/**
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* Clear IPI for a target HART
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*
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@ -25,29 +25,6 @@ void clint_ipi_send(u32 target_hart)
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writel(1, &clint_ipi[target_hart]);
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}
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void clint_ipi_sync(u32 target_hart)
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{
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u32 target_ipi, incoming_ipi;
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u32 source_hart = sbi_current_hartid();
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if (clint_ipi_hart_count <= target_hart)
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return;
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/* Wait until target HART has handled IPI */
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incoming_ipi = 0;
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while (1) {
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target_ipi = readl(&clint_ipi[target_hart]);
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if (!target_ipi)
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break;
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incoming_ipi |=
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atomic_raw_xchg_uint(&clint_ipi[source_hart], 0);
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}
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if (incoming_ipi)
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writel(incoming_ipi, &clint_ipi[source_hart]);
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}
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void clint_ipi_clear(u32 target_hart)
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{
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if (clint_ipi_hart_count <= target_hart)
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@ -185,7 +185,6 @@ const struct sbi_platform_operations platform_ops = {
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.irqchip_init = ariane_irqchip_init,
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.ipi_init = ariane_ipi_init,
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.ipi_send = clint_ipi_send,
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.ipi_sync = clint_ipi_sync,
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.ipi_clear = clint_ipi_clear,
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.timer_init = ariane_timer_init,
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.timer_value = clint_timer_value,
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@ -102,7 +102,6 @@ const struct sbi_platform_operations platform_ops = {
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.ipi_init = k210_ipi_init,
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.ipi_send = clint_ipi_send,
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.ipi_sync = clint_ipi_sync,
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.ipi_clear = clint_ipi_clear,
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.timer_init = k210_timer_init,
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@ -136,7 +136,6 @@ const struct sbi_platform_operations platform_ops = {
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.console_init = sifive_u_console_init,
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.irqchip_init = sifive_u_irqchip_init,
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.ipi_send = clint_ipi_send,
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.ipi_sync = clint_ipi_sync,
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.ipi_clear = clint_ipi_clear,
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.ipi_init = sifive_u_ipi_init,
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.timer_value = clint_timer_value,
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@ -141,7 +141,6 @@ const struct sbi_platform_operations platform_ops = {
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.console_init = virt_console_init,
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.irqchip_init = virt_irqchip_init,
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.ipi_send = clint_ipi_send,
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.ipi_sync = clint_ipi_sync,
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.ipi_clear = clint_ipi_clear,
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.ipi_init = virt_ipi_init,
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.timer_value = clint_timer_value,
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@ -199,7 +199,6 @@ const struct sbi_platform_operations platform_ops = {
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.console_init = fu540_console_init,
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.irqchip_init = fu540_irqchip_init,
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.ipi_send = clint_ipi_send,
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.ipi_sync = clint_ipi_sync,
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.ipi_clear = clint_ipi_clear,
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.ipi_init = fu540_ipi_init,
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.timer_value = clint_timer_value,
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@ -124,15 +124,6 @@ static void platform_ipi_send(u32 target_hart)
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clint_ipi_send(target_hart);
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}
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/*
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* Wait for target HART to acknowledge IPI.
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*/
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static void platform_ipi_sync(u32 target_hart)
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{
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/* Example if the generic CLINT driver is used */
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clint_ipi_sync(target_hart);
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}
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/*
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* Clear IPI for a target HART.
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*/
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@ -216,7 +207,6 @@ const struct sbi_platform_operations platform_ops = {
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.console_init = platform_console_init,
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.irqchip_init = platform_irqchip_init,
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.ipi_send = platform_ipi_send,
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.ipi_sync = platform_ipi_sync,
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.ipi_clear = platform_ipi_clear,
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.ipi_init = platform_ipi_init,
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.timer_value = platform_timer_value,
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