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lib: sbi_hart: clear mip csr during hart init 

If mip.SEIP bit is not cleared then on HiFive Unmatched board it causes
spurious external interrupts. This breaks the boot up of HiFive Unmatched
board. Hence it is required to bring the mip CSR to a known state during
hart init and avoid spurious interrupts.

Fixes: d9e7368 ("firmware: Not to clear all the MIP")
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Mayuresh Chitale 2023-03-25 22:20:47 +05:30 committed by Anup Patel
parent 30b9e7ee14
commit 8e90259da8
2 changed files with 6 additions and 7 deletions
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7
firmware/fw_base.S
View File

@ -430,13 +430,6 @@ _start_warm:
/* Disable all interrupts */
csrw CSR_MIE, zero
/*
* Only clear the MIP_SSIP and MIP_STIP. For the platform like QEMU,
* If we clear other interrupts like MIP_SEIP and the pendings of
* PLIC still exist, the QEMU may not set it back immediately.
*/
li t0, (MIP_SSIP | MIP_STIP)
csrc CSR_MIP, t0
/* Find HART count and HART stack size */
lla a4, platform

6
lib/sbi/sbi_hart.c
View File

@ -733,6 +733,12 @@ int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot)
{
int rc;
/*
* Clear mip CSR before proceeding with init to avoid any spurious
* external interrupts in S-mode.
*/
csr_write(CSR_MIP, 0);
if (cold_boot) {
if (misa_extension('H'))
sbi_hart_expected_trap = &__sbi_expected_trap_hext;