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include: Adjust Sscofpmf mhpmevent mask for upper 6 bits 

Currently, OpenSBI reserves the upper 16 bits in mhpmevent for
the Sscofpmf extension.

However, according to the Sscofpmf extension specification [1],
it only defines the upper 6 bits in mhpmevent for privilege mode
inhibit and counter overflow disable. Other bits are defined by
the platform for event selection.

Since vendors might define raw event encoding exceeding 48 bits in
mhpmevent, we should adjust the MHPMEVENT_SSCOF_MASK to support it.

Link: https://github.com/riscv/riscv-isa-manual [1]
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Reviewed-By: Xiang W <wxjstz@126.com>
Reviewed-By: Anup Patel <anup@brainfault.org>
This commit is contained in:
Eric Lin 2024-07-30 17:30:22 +08:00 committed by Anup Patel
parent bb7267a07f
commit a2807646a8
1 changed files with 1 additions and 1 deletions
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2
include/sbi/riscv_encoding.h
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@ -207,7 +207,7 @@
#endif #endif
#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) #define MHPMEVENT_SSCOF_MASK _ULL(0xFC00000000000000)
#define ENVCFG_STCE (_ULL(1) << 63) #define ENVCFG_STCE (_ULL(1) << 63)
#define ENVCFG_PBMTE (_ULL(1) << 62) #define ENVCFG_PBMTE (_ULL(1) << 62)