lib: utils/irqchip: Add shared MMIO region for PLIC in root domain

On platforms with Smepmp, the MMIO regions accessed by M-mode need
to be explicitly marked with M-mode only read/write or shared (both
(M-mode and S-mode) read/write permission.

If the above is not done then runtime PLIC access from M-mode on
platforms with Smepmp will result in access fault when further
results in CPU hotplug not working.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
This commit is contained in:
Anup Patel 2023-12-11 14:07:56 +05:30 committed by Anup Patel
parent 80169b25f8
commit cdebae2cc9
9 changed files with 21 additions and 1 deletions

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@ -14,6 +14,7 @@
struct plic_data { struct plic_data {
unsigned long addr; unsigned long addr;
unsigned long size;
unsigned long num_src; unsigned long num_src;
}; };

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@ -880,6 +880,7 @@ int fdt_parse_plic_node(void *fdt, int nodeoffset, struct plic_data *plic)
if (rc < 0 || !reg_addr || !reg_size) if (rc < 0 || !reg_addr || !reg_size)
return SBI_ENODEV; return SBI_ENODEV;
plic->addr = reg_addr; plic->addr = reg_addr;
plic->size = reg_size;
val = fdt_getprop(fdt, nodeoffset, "riscv,ndev", &len); val = fdt_getprop(fdt, nodeoffset, "riscv,ndev", &len);
if (len > 0) if (len > 0)

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@ -10,7 +10,9 @@
#include <sbi/riscv_io.h> #include <sbi/riscv_io.h>
#include <sbi/riscv_encoding.h> #include <sbi/riscv_encoding.h>
#include <sbi/sbi_bitops.h>
#include <sbi/sbi_console.h> #include <sbi/sbi_console.h>
#include <sbi/sbi_domain.h>
#include <sbi/sbi_error.h> #include <sbi/sbi_error.h>
#include <sbi/sbi_string.h> #include <sbi/sbi_string.h>
#include <sbi_utils/irqchip/plic.h> #include <sbi_utils/irqchip/plic.h>
@ -171,5 +173,7 @@ int plic_cold_irqchip_init(const struct plic_data *plic)
for (i = 1; i <= plic->num_src; i++) for (i = 1; i <= plic->num_src; i++)
plic_set_priority(plic, i, 0); plic_set_priority(plic, i, 0);
return 0; return sbi_domain_root_add_memrange(plic->addr, plic->size, BIT(20),
(SBI_DOMAIN_MEMREGION_MMIO |
SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW));
} }

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@ -25,6 +25,8 @@
#define ARIANE_UART_REG_WIDTH 4 #define ARIANE_UART_REG_WIDTH 4
#define ARIANE_UART_REG_OFFSET 0 #define ARIANE_UART_REG_OFFSET 0
#define ARIANE_PLIC_ADDR 0xc000000 #define ARIANE_PLIC_ADDR 0xc000000
#define ARIANE_PLIC_SIZE (0x200000 + \
(ARIANE_HART_COUNT * 0x1000))
#define ARIANE_PLIC_NUM_SOURCES 3 #define ARIANE_PLIC_NUM_SOURCES 3
#define ARIANE_HART_COUNT 1 #define ARIANE_HART_COUNT 1
#define ARIANE_CLINT_ADDR 0x2000000 #define ARIANE_CLINT_ADDR 0x2000000
@ -36,6 +38,7 @@
static struct plic_data plic = { static struct plic_data plic = {
.addr = ARIANE_PLIC_ADDR, .addr = ARIANE_PLIC_ADDR,
.size = ARIANE_PLIC_SIZE,
.num_src = ARIANE_PLIC_NUM_SOURCES, .num_src = ARIANE_PLIC_NUM_SOURCES,
}; };

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@ -24,6 +24,8 @@
#define OPENPITON_DEFAULT_UART_REG_WIDTH 1 #define OPENPITON_DEFAULT_UART_REG_WIDTH 1
#define OPENPITON_DEFAULT_UART_REG_OFFSET 0 #define OPENPITON_DEFAULT_UART_REG_OFFSET 0
#define OPENPITON_DEFAULT_PLIC_ADDR 0xfff1100000 #define OPENPITON_DEFAULT_PLIC_ADDR 0xfff1100000
#define OPENPITON_DEFAULT_PLIC_SIZE (0x200000 + \
(OPENPITON_DEFAULT_HART_COUNT * 0x1000))
#define OPENPITON_DEFAULT_PLIC_NUM_SOURCES 2 #define OPENPITON_DEFAULT_PLIC_NUM_SOURCES 2
#define OPENPITON_DEFAULT_HART_COUNT 3 #define OPENPITON_DEFAULT_HART_COUNT 3
#define OPENPITON_DEFAULT_CLINT_ADDR 0xfff1020000 #define OPENPITON_DEFAULT_CLINT_ADDR 0xfff1020000
@ -40,6 +42,7 @@ static struct platform_uart_data uart = {
}; };
static struct plic_data plic = { static struct plic_data plic = {
.addr = OPENPITON_DEFAULT_PLIC_ADDR, .addr = OPENPITON_DEFAULT_PLIC_ADDR,
.size = OPENPITON_DEFAULT_PLIC_SIZE,
.num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES, .num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES,
}; };

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@ -32,6 +32,7 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
static struct plic_data plic = { static struct plic_data plic = {
.addr = K210_PLIC_BASE_ADDR, .addr = K210_PLIC_BASE_ADDR,
.size = K210_PLIC_BASE_SIZE,
.num_src = K210_PLIC_NUM_SOURCES, .num_src = K210_PLIC_NUM_SOURCES,
}; };

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@ -27,6 +27,7 @@
#define K210_ACLINT_MTIMER_ADDR \ #define K210_ACLINT_MTIMER_ADDR \
(K210_CLINT_BASE_ADDR + CLINT_MTIMER_OFFSET) (K210_CLINT_BASE_ADDR + CLINT_MTIMER_OFFSET)
#define K210_PLIC_BASE_ADDR 0x0C000000ULL #define K210_PLIC_BASE_ADDR 0x0C000000ULL
#define K210_PLIC_BASE_SIZE (0x200000ULL + (K210_HART_COUNT * 0x1000))
/* Registers */ /* Registers */
#define K210_PLL0 0x08 #define K210_PLL0 0x08

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@ -39,6 +39,8 @@
CLINT_MTIMER_OFFSET) CLINT_MTIMER_OFFSET)
#define UX600_PLIC_ADDR 0x8000000 #define UX600_PLIC_ADDR 0x8000000
#define UX600_PLIC_SIZE (0x200000 + \
(UX600_HART_COUNT * 0x1000))
#define UX600_PLIC_NUM_SOURCES 0x35 #define UX600_PLIC_NUM_SOURCES 0x35
#define UX600_PLIC_NUM_PRIORITIES 7 #define UX600_PLIC_NUM_PRIORITIES 7
@ -63,6 +65,7 @@ static u32 ux600_clk_freq = 8000000;
static struct plic_data plic = { static struct plic_data plic = {
.addr = UX600_PLIC_ADDR, .addr = UX600_PLIC_ADDR,
.size = UX600_PLIC_SIZE,
.num_src = UX600_PLIC_NUM_SOURCES, .num_src = UX600_PLIC_NUM_SOURCES,
}; };

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@ -19,6 +19,8 @@
#include <sbi_utils/timer/aclint_mtimer.h> #include <sbi_utils/timer/aclint_mtimer.h>
#define PLATFORM_PLIC_ADDR 0xc000000 #define PLATFORM_PLIC_ADDR 0xc000000
#define PLATFORM_PLIC_SIZE (0x200000 + \
(PLATFORM_HART_COUNT * 0x1000))
#define PLATFORM_PLIC_NUM_SOURCES 128 #define PLATFORM_PLIC_NUM_SOURCES 128
#define PLATFORM_HART_COUNT 4 #define PLATFORM_HART_COUNT 4
#define PLATFORM_CLINT_ADDR 0x2000000 #define PLATFORM_CLINT_ADDR 0x2000000
@ -33,6 +35,7 @@
static struct plic_data plic = { static struct plic_data plic = {
.addr = PLATFORM_PLIC_ADDR, .addr = PLATFORM_PLIC_ADDR,
.size = PLATFORM_PLIC_SIZE,
.num_src = PLATFORM_PLIC_NUM_SOURCES, .num_src = PLATFORM_PLIC_NUM_SOURCES,
}; };