platform: generic: andes: Refine Andes PMA related code
This patch refines the Andes PMA related code. The main change is refactor andes_pma_[read|write]_cfg() and andes_pma_[read|write]_addr() into new functions andes_pma_[read|write]_num(). Also, fix some coding style problems. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Ben Zong-You Xie
Anup Patel
parent
7830e98785
commit
f09f16430a
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@ -1,12 +1,10 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*
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* Copyright (c) 2020 Andes Technology Corporation
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* Copyright (c) 2024 Andes Technology Corporation
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*
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* Authors:
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* Nick Hu <nickhu@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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* Ben Zong-You Xie <ben717@andestech.com>
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* Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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*/
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@ -19,124 +17,81 @@
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#include <sbi/sbi_error.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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static inline unsigned long andes_pma_read_cfg(unsigned int pma_cfg_off)
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static unsigned long andes_pma_read_num(unsigned int csr_num)
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{
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#define switchcase_pma_cfg_read(__pma_cfg_off, __val) \
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case __pma_cfg_off: \
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__val = csr_read(__pma_cfg_off); \
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#define switchcase_csr_read(__csr_num, __val) \
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case __csr_num: \
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__val = csr_read(__csr_num); \
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break;
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#define switchcase_pma_cfg_read_2(__pma_cfg_off, __val) \
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switchcase_pma_cfg_read(__pma_cfg_off + 0, __val) \
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switchcase_pma_cfg_read(__pma_cfg_off + 2, __val)
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#define switchcase_csr_read_2(__csr_num, __val) \
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switchcase_csr_read(__csr_num + 0, __val) \
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switchcase_csr_read(__csr_num + 1, __val)
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#define switchcase_csr_read_4(__csr_num, __val) \
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switchcase_csr_read_2(__csr_num + 0, __val) \
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switchcase_csr_read_2(__csr_num + 2, __val)
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#define switchcase_csr_read_8(__csr_num, __val) \
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switchcase_csr_read_4(__csr_num + 0, __val) \
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switchcase_csr_read_4(__csr_num + 4, __val)
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#define switchcase_csr_read_16(__csr_num, __val) \
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switchcase_csr_read_8(__csr_num + 0, __val) \
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switchcase_csr_read_8(__csr_num + 8, __val)
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unsigned long ret = 0;
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switch (pma_cfg_off) {
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switchcase_pma_cfg_read_2(CSR_PMACFG0, ret)
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switch (csr_num) {
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switchcase_csr_read_4(CSR_PMACFG0, ret)
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switchcase_csr_read_16(CSR_PMAADDR0, ret)
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default:
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sbi_panic("%s: Unknown PMA CFG offset %#x", __func__, pma_cfg_off);
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sbi_panic("%s: Unknown Andes PMA CSR %#x", __func__, csr_num);
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break;
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}
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return ret;
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#undef switchcase_pma_cfg_read_2
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#undef switchcase_pma_cfg_read
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#undef switchcase_csr_read_16
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#undef switchcase_csr_read_8
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#undef switchcase_csr_read_4
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#undef switchcase_csr_read_2
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#undef switchcase_csr_read
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}
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static inline void andes_pma_write_cfg(unsigned int pma_cfg_off, unsigned long val)
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static void andes_pma_write_num(unsigned int csr_num, unsigned long val)
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{
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#define switchcase_pma_cfg_write(__pma_cfg_off, __val) \
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case __pma_cfg_off: \
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csr_write(__pma_cfg_off, __val); \
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#define switchcase_csr_write(__csr_num, __val) \
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case __csr_num: \
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csr_write(__csr_num, __val); \
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break;
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#define switchcase_pma_cfg_write_2(__pma_cfg_off, __val) \
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switchcase_pma_cfg_write(__pma_cfg_off + 0, __val) \
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switchcase_pma_cfg_write(__pma_cfg_off + 2, __val)
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switch (pma_cfg_off) {
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switchcase_pma_cfg_write_2(CSR_PMACFG0, val)
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#define switchcase_csr_write_2(__csr_num, __val) \
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switchcase_csr_write(__csr_num + 0, __val) \
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switchcase_csr_write(__csr_num + 1, __val)
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#define switchcase_csr_write_4(__csr_num, __val) \
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switchcase_csr_write_2(__csr_num + 0, __val) \
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switchcase_csr_write_2(__csr_num + 2, __val)
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#define switchcase_csr_write_8(__csr_num, __val) \
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switchcase_csr_write_4(__csr_num + 0, __val) \
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switchcase_csr_write_4(__csr_num + 4, __val)
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#define switchcase_csr_write_16(__csr_num, __val) \
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switchcase_csr_write_8(__csr_num + 0, __val) \
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switchcase_csr_write_8(__csr_num + 8, __val)
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switch (csr_num) {
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switchcase_csr_write_4(CSR_PMACFG0, val)
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switchcase_csr_write_16(CSR_PMAADDR0, val)
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default:
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sbi_panic("%s: Unknown PMA CFG offset %#x", __func__, pma_cfg_off);
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sbi_panic("%s: Unknown Andes PMA CSR %#x", __func__, csr_num);
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break;
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}
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#undef switchcase_pma_cfg_write_2
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#undef switchcase_pma_cfg_write
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#undef switchcase_csr_write_16
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#undef switchcase_csr_write_8
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#undef switchcase_csr_write_4
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#undef switchcase_csr_write_2
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#undef switchcase_csr_write
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}
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static inline void andes_pma_write_addr(unsigned int pma_addr_off, unsigned long val)
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static inline bool not_napot(unsigned long addr, unsigned long size)
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{
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#define switchcase_pma_write(__pma_addr_off, __val) \
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case __pma_addr_off: \
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csr_write(__pma_addr_off, __val); \
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break;
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#define switchcase_pma_write_2(__pma_addr_off, __val) \
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switchcase_pma_write(__pma_addr_off + 0, __val) \
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switchcase_pma_write(__pma_addr_off + 1, __val)
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#define switchcase_pma_write_4(__pma_addr_off, __val) \
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switchcase_pma_write_2(__pma_addr_off + 0, __val) \
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switchcase_pma_write_2(__pma_addr_off + 2, __val)
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#define switchcase_pma_write_8(__pma_addr_off, __val) \
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switchcase_pma_write_4(__pma_addr_off + 0, __val) \
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switchcase_pma_write_4(__pma_addr_off + 4, __val)
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#define switchcase_pma_write_16(__pma_addr_off, __val) \
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switchcase_pma_write_8(__pma_addr_off + 0, __val) \
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switchcase_pma_write_8(__pma_addr_off + 8, __val)
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switch (pma_addr_off) {
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switchcase_pma_write_16(CSR_PMAADDR0, val)
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default:
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sbi_panic("%s: Unknown PMA ADDR offset %#x", __func__, pma_addr_off);
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break;
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}
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#undef switchcase_pma_write_16
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#undef switchcase_pma_write_8
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#undef switchcase_pma_write_4
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#undef switchcase_pma_write_2
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#undef switchcase_pma_write
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}
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static inline unsigned long andes_pma_read_addr(unsigned int pma_addr_off)
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{
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#define switchcase_pma_read(__pma_addr_off, __val) \
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case __pma_addr_off: \
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__val = csr_read(__pma_addr_off); \
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break;
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#define switchcase_pma_read_2(__pma_addr_off, __val) \
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switchcase_pma_read(__pma_addr_off + 0, __val) \
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switchcase_pma_read(__pma_addr_off + 1, __val)
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#define switchcase_pma_read_4(__pma_addr_off, __val) \
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switchcase_pma_read_2(__pma_addr_off + 0, __val) \
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switchcase_pma_read_2(__pma_addr_off + 2, __val)
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#define switchcase_pma_read_8(__pma_addr_off, __val) \
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switchcase_pma_read_4(__pma_addr_off + 0, __val) \
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switchcase_pma_read_4(__pma_addr_off + 4, __val)
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#define switchcase_pma_read_16(__pma_addr_off, __val) \
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switchcase_pma_read_8(__pma_addr_off + 0, __val) \
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switchcase_pma_read_8(__pma_addr_off + 8, __val)
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unsigned long ret = 0;
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switch (pma_addr_off) {
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switchcase_pma_read_16(CSR_PMAADDR0, ret)
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default:
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sbi_panic("%s: Unknown PMA ADDR offset %#x", __func__, pma_addr_off);
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break;
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}
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return ret;
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#undef switchcase_pma_read_16
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#undef switchcase_pma_read_8
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#undef switchcase_pma_read_4
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#undef switchcase_pma_read_2
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#undef switchcase_pma_read
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return ((size & (size - 1)) || (addr & (size - 1)));
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}
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static unsigned long andes_pma_setup(const struct andes_pma_region *pma_region,
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@ -149,36 +104,24 @@ static unsigned long andes_pma_setup(const struct andes_pma_region *pma_region,
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unsigned long pmaaddr;
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char *pmaxcfg;
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/* Check for 4KiB granularity */
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if (size < (1 << 12))
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/* Check for a 4KiB granularity NAPOT region*/
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if (size < ANDES_PMA_GRANULARITY || not_napot(addr, size) ||
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!(pma_region->flags & ANDES_PMACFG_ETYP_NAPOT))
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return SBI_EINVAL;
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/* Check size is power of 2 */
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if (size & (size - 1))
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return SBI_EINVAL;
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if (entry_id > 15)
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return SBI_EINVAL;
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if (!(pma_region->flags & ANDES_PMACFG_ETYP_NAPOT))
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return SBI_EINVAL;
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if ((addr & (size - 1)) != 0)
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return SBI_EINVAL;
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pma_cfg_addr = entry_id / 8 ? CSR_PMACFG0 + 2 : CSR_PMACFG0;
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pmacfg_val = andes_pma_read_cfg(pma_cfg_addr);
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pma_cfg_addr = CSR_PMACFG0 + ((entry_id / 8) ? 2 : 0);
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pmacfg_val = andes_pma_read_num(pma_cfg_addr);
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pmaxcfg = (char *)&pmacfg_val + (entry_id % 8);
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*pmaxcfg = 0;
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*pmaxcfg = pma_region->flags;
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andes_pma_write_cfg(pma_cfg_addr, pmacfg_val);
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andes_pma_write_num(pma_cfg_addr, pmacfg_val);
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pmaaddr = (addr >> 2) + (size >> 3) - 1;
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andes_pma_write_addr(CSR_PMAADDR0 + entry_id, pmaaddr);
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andes_pma_write_num(CSR_PMAADDR0 + entry_id, pmaaddr);
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return andes_pma_read_addr(CSR_PMAADDR0 + entry_id) == pmaaddr ?
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return andes_pma_read_num(CSR_PMAADDR0 + entry_id) == pmaaddr ?
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pmaaddr : SBI_EINVAL;
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}
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@ -202,19 +145,20 @@ static int andes_fdt_pma_resv(void *fdt, const struct andes_pma_region *pma,
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if (na > 1 && addr_high) {
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sbi_snprintf(name, sizeof(name),
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"pma_resv%d@%x,%x", index,
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addr_high, addr_low);
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"pma_resv%d@%x,%x",
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index, addr_high, addr_low);
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} else {
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sbi_snprintf(name, sizeof(name),
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"pma_resv%d@%x", index,
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addr_low);
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"pma_resv%d@%x",
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index, addr_low);
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}
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subnode = fdt_add_subnode(fdt, parent, name);
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if (subnode < 0)
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return subnode;
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if (pma->shared_dma) {
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err = fdt_setprop_string(fdt, subnode, "compatible", "shared-dma-pool");
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err = fdt_setprop_string(fdt, subnode, "compatible",
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"shared-dma-pool");
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if (err < 0)
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return err;
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}
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@ -259,14 +203,14 @@ static int andes_fdt_reserved_memory_fixup(void *fdt,
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{
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int parent;
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/* try to locate the reserved memory node */
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/* Try to locate the reserved memory node */
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parent = fdt_path_offset(fdt, "/reserved-memory");
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if (parent < 0) {
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int na = fdt_address_cells(fdt, 0);
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int ns = fdt_size_cells(fdt, 0);
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int err;
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/* if such node does not exist, create one */
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/* If such node does not exist, create one */
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parent = fdt_add_subnode(fdt, 0, "reserved-memory");
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if (parent < 0)
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return parent;
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@ -307,17 +251,13 @@ int andes_pma_setup_regions(const struct andes_pma_region *pma_regions,
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return SBI_ENOTSUPP;
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/* Configure the PMA regions */
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dt_populate_cnt = 0;
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for (i = 0; i < pma_regions_count; i++) {
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pa = andes_pma_setup(&pma_regions[i], i);
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if (pa == SBI_EINVAL)
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return SBI_EINVAL;
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}
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dt_populate_cnt = 0;
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for (i = 0; i < pma_regions_count; i++) {
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if (!pma_regions[i].dt_populate)
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continue;
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dt_populate_cnt++;
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else if (pma_regions[i].dt_populate)
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dt_populate_cnt++;
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}
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if (!dt_populate_cnt)
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@ -325,7 +265,8 @@ int andes_pma_setup_regions(const struct andes_pma_region *pma_regions,
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fdt = fdt_get_address();
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ret = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + (64 * dt_populate_cnt));
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ret = fdt_open_into(fdt, fdt,
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fdt_totalsize(fdt) + (64 * dt_populate_cnt));
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if (ret < 0)
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return ret;
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@ -333,7 +274,9 @@ int andes_pma_setup_regions(const struct andes_pma_region *pma_regions,
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if (!pma_regions[i].dt_populate)
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continue;
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ret = andes_fdt_reserved_memory_fixup(fdt, &pma_regions[i], j++);
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ret = andes_fdt_reserved_memory_fixup(fdt,
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&pma_regions[i],
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j++);
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if (ret)
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return ret;
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}
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@ -10,6 +10,8 @@
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#define ANDES_MAX_PMA_REGIONS 16
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#define ANDES_PMA_GRANULARITY (1 << 12)
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/* Naturally aligned power of 2 region */
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#define ANDES_PMACFG_ETYP_NAPOT 3
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