The fdt_cpu_fixup() should work fine even if HARTs without MMU
are not marked invalid by platform support code.
In future, we plan to treat HARTs without MMU as valid in the
generic platform support so that we can hold these HARTs in
HSM STOPPED state.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
The SBI_HART_HAS_PMP feature is redundant because we already
have number of PMP regions returned by sbi_hart_pmp_count().
Checking whether PMP is supported for a HART can be simply done
by checking non-zero value returned by sbi_hart_pmp_count().
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Use strncmp instead of using sbi_strcmp directly in fdt_parse_hart_id()
to allow compiling fdt_helper.c by external firmware.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Currently 256 bytes is used for the FDT expand size when fixing up
reserved memory node. Increase it to 1024 bytes with an estimated
size of 64 bytes per PMP memory region by 16 regions in total.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
C-Class is a member of the SHAKTI family of processors from Indian
Institute of Technology - Madras(IIT-M).
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md
We add OpenSBI support for Shakti C-class SoC.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This is achieved by removing the 'no-map' property from the
'reserved-memory' node when PMP is present, otherwise we keep it as it
offers a small protection if the OS does not map this region at all.
A new callback in platform_override is introduced and allows to fixup the
device-tree. It is used here to override this new default behaviour on
SiFive Fu540 platforms that has an erratum that prevents S-mode software
to access a PMP protected region using 1GB page table mapping.
If PMP is present, telling the OS not to map the reserved regions does not
add much protection since it only avoids access to regions that are already
protected by PMP. But by not allowing the OS to map those regions, it
creates holes in the OS system memory map and prevents the use of
hugepages which would generate, among other benefits, less TLB miss.
Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
We can have multiple matching DT nodes of the same FDT timer driver
so in this case we should call cold_init() for all matching DT nodes
instead of just first matching DT node.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We can have multiple matching DT nodes of the same FDT ipi driver
so in this case we should call cold_init() for all matching DT nodes
instead of just first matching DT node.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We add fdt_parse_clint_node() function which will be used by
fdt_ipi_clint and fdt_timer_clint drivers to parse CLINT details
from DT node.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We extend CLINT cold init function to have a "struct clint_data *"
parameter pointing to CLINT details. This allows platforms to use
CLINT functions for multiple CLINT instances.
When multiple CLINTs are present, the platform can also provide
one of the CLINT as reference CLINT for other CLINTs. This will
help CLINTs to sync their time value with reference CLINT using
a time_delta computed in warm init function.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We can have multiple matching DT nodes of the same FDT irqchip
driver so in this case we should call cold_init() for all matching
DT nodes instead of just first matching DT node.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We extend fdt_find_match() implementation by adding node offset
parameter which represents the first node to match from.
The improved fdt_find_match() can be used to find multiple
match nodes.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We extend all PLIC functions to have a "struct plic_data *"
parameter pointing to PLIC details. This allows platforms to
use these functions for multiple PLIC instances.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
The "target_hart" and "hart_count" parameters of PLIC cold and
warm init functions are only used for sanity checks and not
required in PLIC initialization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
It is not mandatory for a RISC-V systems to implement all PMP
regions so we have to check all PMPADDRx CSRs to determine excat
number of supported PMP regions.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
It makes more sense to have scratch pointer as parameter in
HART feature APIs because:
1. We already have scratch pointer at places where these APIs
are used.
2. This is consistent with lot of other APIs in sbi_hart.h
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
PMP & performance counters belong to a hart rather than a platform.
In addition to that, these features enable reading/writing from a
particular csr. Thus, they can be detected and set at runtime rather
than compile time.
Move PMP/MCOUNTEREN/SCOUNTEREN features to hart and detect them at runtime.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
As per RISC-V ISA, pmp is not mandatory. Currently, we only add reserved
memory node in DT only if PMP is present. That allows supervisor to access
the memory where OpenSBI continue to exist without realizing it for non-pmp
based platforms. It may result in corrupting OpenSBI. That's why OpenSBI
should at least let the supervisor know where it continue to exist.
This a best effort service provided by OpenSBI expecting that supervisor
software is not buggy and properly sets up its memory after parsing the
reserved-memory device tree node.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
We add simple reset framework which will select and use reset driver
based on details in FDT passed by previous booting stage.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We add simple serial framework which will select and use serial driver
based on details in FDT passed by previous booting stage.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We add simple irqchip framework which will select and use irqchip driver
based on details in FDT passed by previous booting stage.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We add simple ipi framework which will select and use ipi driver
based on details in FDT passed by previous booting stage.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We add simple timer framework which will select and use timer driver
based on details in FDT passed by previous booting stage.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We add fdt_parse_plic_node() function which will allow us to parse
a particular DT node as PLIC node. This will be useful in parsing
the DT node which we have found by matching compatible string.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We add fdt_parse_max_hart_id() API which return max HART id based
on CPU DT nodes. This will be used by generic FDT based drivers in
subsequent patches.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Parsing HART id from a CPU DT node is a common requirement for
RISC-V systems. The newly added fdt_parse_hart_id() also helps
reduce duplicate code between fdt_cpu_fixup() function and
fdt_parse_hart_count() function.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
We add fdt_parse_sifive_uart_node() function which will allow
us to parse a particular DT node as SiFive UART node. This will
be useful in parsing the node pointed by stdout-path.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
The fdt_get_node_addr_size() will be useful in FDT based simple
driver frameworks so we make it a public function.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
This patch adds FDT match table based node lookup funcitons.
These functions will be useful in implementing simple FDT
based driver frameworks.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
The fdt_parse_clint() is quite generic and can be used for other
types of devices so we rename it to fdt_parse_compat_addr().
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We add fdt_parse_uart8250_node() function which will allow us
to parse a particular DT node as UART 8250 node. This will be
useful in parsing the node pointed by stdout-path.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
The information parsed by fdt_parse_uart8250() API is not complete.
We need to parse reg-shift and reg-io-width for UART 8520 as well.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
We should skip baudrate config for UART8250 and SiFive UART when
input frequency is zero.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
This patch factor-out SiFive test device related stuff into
it's own source file from qemu/virt platform. In future, we
can find SiFive test device address from device tree as well.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
We can achieve shutdown, cold reboot, and warm reboot using just
one sbi_platform callback so we combine system_reboot() and
system_shutdown() callbacks into one system_reset() callback.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
As per the PLIC specification, maximum priority threshold value is 0x7.
Even though, writing a higher value doesn't cause any error in qemu
hifive unleashed, there may be some implementation which checks the upper
and may result in an illegal access.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Currently, the fdt_cpu_fixup() implementation assumes:
1. We have one CPU DT for each HART under /cpus DT node
2. The CPU DT nodes are named sequentially (i.e cpu@0,
cpu@1, ...) which is not true for discontinuous and
sparse HART ids (i.e. cpu@0, cpu@4, cpu@5). Generally,
CPU DT node are named based on HART id and not HART
index
If any of the above assumptions are violated then the
fdt_cpu_fixup() will not work.
This improves fdt_cpu_fixup() implementation and makes
it independent of above assumptions.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
FDT helper file contain both fdt fixup and parsing functions.
Split the fixup related functions to a separate file for a better code
organization.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Different DT based platforms from the sam family may reuse IP blocks with
different configurations. These different configurations can be obtained
by parsing the device tree.
Add a FDT parser framework that can parse various device configurations from
device tree. Currently, the parsing algorithms doesn't cover all the use cases
or possible combination of DT configurations. It will be improved over time.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
A platform can have discontinuous and/or sparse HART ids so we
cannot always assume a set of HARTs with continuous HART ids.
This patch adds support for discontinuous and sparse HART ids by
introducing HART index to HART id table. This table has platform
hart_count entries and it maps HART index to HART id.
The HART index to HART id table has only two restrictions:
1. HART index < sbi_platform hart_count
2. HART id < SBI_HARTMASK_MAX_BITS
Example1:
Let's say we have a platform with 2 HART ids 11 and 22, for such a
a platform:
hart_count = 2
hart_index2id[0] = 11
hart_index2id[1] = 22
Example2:
Let's say we have a platform with 5 HARTs ids 0, 1, 2, 3, and 4
but out of these HART with id 0 is not usable so for such a platform:
hart_count = 5
hart_index2id[0] = -1U
hart_index2id[1] = 1
hart_index2id[2] = 2
hart_index2id[3] = 3
hart_index2id[4] = 4
OR
hart_count = 4
hart_index2id[0] = 1
hart_index2id[1] = 2
hart_index2id[2] = 3
hart_index2id[3] = 4
With HART index to HART id table in place, the hart_disabled()
callback is now redundant so we remove it as well.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
This adds a general device tree fix-up helper to do all required
device tree fix-ups for a typical platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Add a helper routine to updates the "status" property of a CPU node
in the device tree to "disabled" if that hart is in disabled state.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Now that we have a dedicated fdt_helper.c file for DT releated
helper routines, move plic_fdt_fixup() codes from plic.c to
fdt_helper.c and rename it to fdt_plic_fixup() at the same time,
to keep name consistency in the same file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Add a helper routine to insert a child node of the reserved memory
node in the device tree that describes the protected memory region
done by OpenSBI via PMP.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Pull fdt_addresses.o in for fdt_address_cells() & fdt_size_cells().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
The sbi_current_hartid() being a regular function is quite
expensive because for callers it is a function call instead
of a direct CSR read. This patch converts sbi_current_hartid()
into a macro in riscv_asm.h.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Add two macros in preparation to sync libfdt codes to latest v1.5.1
release from upstream.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This fixes various coding style issues found in the serial codes.
No functional changes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Anup Patel