172 lines
4.7 KiB
C
172 lines
4.7 KiB
C
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright 2018 Canaan Inc.
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* Universal Asynchronous Receiver/Transmitter (UART)
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* The UART peripheral supports the following features:
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*
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* - 8-N-1 and 8-N-2 formats: 8 data bits, no parity bit, 1 start
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* bit, 1 or 2 stop bits
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*
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* - 8-entry transmit and receive FIFO buffers with programmable
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* watermark interrupts
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*
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* - 16× Rx oversampling with 2/3 majority voting per bit
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*
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* The UART peripheral does not support hardware flow control or
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* other modem control signals, or synchronous serial data
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* tranfesrs.
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*
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* UART RAM Layout
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* | Address | Name | Description |
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* |-----------|----------|---------------------------------|
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* | 0x000 | txdata | Transmit data register |
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* | 0x004 | rxdata | Receive data register |
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* | 0x008 | txctrl | Transmit control register |
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* | 0x00C | rxctrl | Receive control register |
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* | 0x010 | ie | UART interrupt enable |
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* | 0x014 | ip | UART Interrupt pending |
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* | 0x018 | div | Baud rate divisor |
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*/
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#ifndef _K210_UARTHS_H_
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#define _K210_UARTHS_H_
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#include <sbi/sbi_types.h>
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/* clang-format off */
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/* Base register address */
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#define UARTHS_BASE_ADDR (0x38000000U)
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/* Register address offsets */
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#define UARTHS_REG_TXFIFO 0x00
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#define UARTHS_REG_RXFIFO 0x04
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#define UARTHS_REG_TXCTRL 0x08
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#define UARTHS_REG_RXCTRL 0x0c
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#define UARTHS_REG_IE 0x10
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#define UARTHS_REG_IP 0x14
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#define UARTHS_REG_DIV 0x18
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/* TXCTRL register */
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#define UARTHS_TXEN 0x01
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#define UARTHS_TXWM(x) (((x) & 0xffff) << 16)
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/* RXCTRL register */
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#define UARTHS_RXEN 0x01
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#define UARTHS_RXWM(x) (((x) & 0xffff) << 16)
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/* IP register */
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#define UARTHS_IP_TXWM 0x01
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#define UARTHS_IP_RXWM 0x02
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/* clang-format on */
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struct uarths_txdata {
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/* Bits [7:0] is data */
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u32 data : 8;
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/* Bits [30:8] is 0 */
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u32 zero : 23;
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/* Bit 31 is full status */
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u32 full : 1;
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} __attribute__((packed, aligned(4)));
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struct uarths_rxdata {
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/* Bits [7:0] is data */
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u32 data : 8;
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/* Bits [30:8] is 0 */
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u32 zero : 23;
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/* Bit 31 is empty status */
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u32 empty : 1;
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} __attribute__((packed, aligned(4)));
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struct uarths_txctrl {
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/* Bit 0 is txen, controls whether the Tx channel is active. */
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u32 txen : 1;
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/* Bit 1 is nstop, 0 for one stop bit and 1 for two stop bits */
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u32 nstop : 1;
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/* Bits [15:2] is reserved */
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u32 resv0 : 14;
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/* Bits [18:16] is threshold of interrupt triggers */
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u32 txcnt : 3;
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/* Bits [31:19] is reserved */
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u32 resv1 : 13;
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} __attribute__((packed, aligned(4)));
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struct uarths_rxctrl {
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/* Bit 0 is txen, controls whether the Tx channel is active. */
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u32 rxen : 1;
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/* Bits [15:1] is reserved */
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u32 resv0 : 15;
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/* Bits [18:16] is threshold of interrupt triggers */
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u32 rxcnt : 3;
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/* Bits [31:19] is reserved */
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u32 resv1 : 13;
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} __attribute__((packed, aligned(4)));
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struct uarths_ip {
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/* Bit 0 is txwm, raised less than txcnt */
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u32 txwm : 1;
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/* Bit 1 is txwm, raised greater than rxcnt */
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u32 rxwm : 1;
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/* Bits [31:2] is 0 */
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u32 zero : 30;
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} __attribute__((packed, aligned(4)));
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struct uarths_ie {
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/* Bit 0 is txwm, raised less than txcnt */
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u32 txwm : 1;
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/* Bit 1 is txwm, raised greater than rxcnt */
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u32 rxwm : 1;
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/* Bits [31:2] is 0 */
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u32 zero : 30;
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} __attribute__((packed, aligned(4)));
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struct uarths_div {
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/* Bits [31:2] is baud rate divisor register */
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u32 div : 16;
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/* Bits [31:16] is 0 */
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u32 zero : 16;
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} __attribute__((packed, aligned(4)));
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struct uarths {
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/* Address offset 0x00 */
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struct uarths_txdata txdata;
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/* Address offset 0x04 */
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struct uarths_rxdata rxdata;
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/* Address offset 0x08 */
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struct uarths_txctrl txctrl;
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/* Address offset 0x0c */
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struct uarths_rxctrl rxctrl;
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/* Address offset 0x10 */
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struct uarths_ie ie;
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/* Address offset 0x14 */
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struct uarths_ip ip;
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/* Address offset 0x18 */
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struct uarths_div div;
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} __attribute__((packed, aligned(4)));
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enum uarths_stopbit { UARTHS_STOP_1, UARTHS_STOP_2 };
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void uarths_init(u32 baud_rate, enum uarths_stopbit stopbit);
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void uarths_putc(char c);
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int uarths_getc(void);
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#endif /* _K210_UARTHS_H_ */
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