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The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
21 lines
361 B
C
21 lines
361 B
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 SiFive Inc.
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*/
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#ifndef __FDT_HSM_SIFIVE_INST_H__
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#define __FDT_HSM_SIFIVE_INST_H__
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static inline void sifive_cease(void)
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{
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__asm__ __volatile__(".insn 0x30500073" ::: "memory");
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}
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static inline void sifive_cflush(void)
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{
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__asm__ __volatile__(".insn 0xfc000073" ::: "memory");
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}
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#endif
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