410 lines
13 KiB
C
410 lines
13 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __SBI_ECALL_INTERFACE_H__
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#define __SBI_ECALL_INTERFACE_H__
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/* clang-format off */
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/* SBI Extension IDs */
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#define SBI_EXT_0_1_SET_TIMER 0x0
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#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
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#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
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#define SBI_EXT_0_1_CLEAR_IPI 0x3
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#define SBI_EXT_0_1_SEND_IPI 0x4
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#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
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#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
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#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
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#define SBI_EXT_0_1_SHUTDOWN 0x8
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#define SBI_EXT_BASE 0x10
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#define SBI_EXT_TIME 0x54494D45
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#define SBI_EXT_IPI 0x735049
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#define SBI_EXT_RFENCE 0x52464E43
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#define SBI_EXT_HSM 0x48534D
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#define SBI_EXT_SRST 0x53525354
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#define SBI_EXT_PMU 0x504D55
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#define SBI_EXT_DBCN 0x4442434E
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#define SBI_EXT_SUSP 0x53555350
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#define SBI_EXT_CPPC 0x43505043
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#define SBI_EXT_DBTR 0x44425452
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#define SBI_EXT_SSE 0x535345
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/* SBI function IDs for BASE extension*/
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#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
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#define SBI_EXT_BASE_GET_IMP_ID 0x1
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#define SBI_EXT_BASE_GET_IMP_VERSION 0x2
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#define SBI_EXT_BASE_PROBE_EXT 0x3
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#define SBI_EXT_BASE_GET_MVENDORID 0x4
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#define SBI_EXT_BASE_GET_MARCHID 0x5
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#define SBI_EXT_BASE_GET_MIMPID 0x6
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/* SBI function IDs for TIME extension*/
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#define SBI_EXT_TIME_SET_TIMER 0x0
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/* SBI function IDs for IPI extension*/
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#define SBI_EXT_IPI_SEND_IPI 0x0
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/* SBI function IDs for RFENCE extension*/
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#define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0
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#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1
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#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2
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#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x3
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#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x4
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#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x5
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#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x6
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/* SBI function IDs for HSM extension */
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#define SBI_EXT_HSM_HART_START 0x0
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#define SBI_EXT_HSM_HART_STOP 0x1
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#define SBI_EXT_HSM_HART_GET_STATUS 0x2
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#define SBI_EXT_HSM_HART_SUSPEND 0x3
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#define SBI_HSM_STATE_STARTED 0x0
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#define SBI_HSM_STATE_STOPPED 0x1
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#define SBI_HSM_STATE_START_PENDING 0x2
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#define SBI_HSM_STATE_STOP_PENDING 0x3
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#define SBI_HSM_STATE_SUSPENDED 0x4
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#define SBI_HSM_STATE_SUSPEND_PENDING 0x5
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#define SBI_HSM_STATE_RESUME_PENDING 0x6
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#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
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#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
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#define SBI_HSM_SUSP_PLAT_BASE 0x10000000
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#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
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#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
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#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
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#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
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#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
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SBI_HSM_SUSP_PLAT_BASE)
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#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
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SBI_HSM_SUSP_BASE_MASK)
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/* SBI function IDs for SRST extension */
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#define SBI_EXT_SRST_RESET 0x0
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#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
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#define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
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#define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
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#define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT
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#define SBI_SRST_RESET_REASON_NONE 0x0
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#define SBI_SRST_RESET_REASON_SYSFAIL 0x1
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/* SBI function IDs for PMU extension */
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#define SBI_EXT_PMU_NUM_COUNTERS 0x0
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#define SBI_EXT_PMU_COUNTER_GET_INFO 0x1
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#define SBI_EXT_PMU_COUNTER_CFG_MATCH 0x2
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#define SBI_EXT_PMU_COUNTER_START 0x3
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#define SBI_EXT_PMU_COUNTER_STOP 0x4
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#define SBI_EXT_PMU_COUNTER_FW_READ 0x5
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#define SBI_EXT_PMU_COUNTER_FW_READ_HI 0x6
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#define SBI_EXT_PMU_SNAPSHOT_SET_SHMEM 0x7
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/* SBI function IDs for DBTR extension */
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#define SBI_EXT_DBTR_NUM_TRIGGERS 0x0
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#define SBI_EXT_DBTR_SETUP_SHMEM 0x1
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#define SBI_EXT_DBTR_TRIGGER_READ 0x2
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#define SBI_EXT_DBTR_TRIGGER_INSTALL 0x3
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#define SBI_EXT_DBTR_TRIGGER_UPDATE 0x4
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#define SBI_EXT_DBTR_TRIGGER_UNINSTALL 0x5
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#define SBI_EXT_DBTR_TRIGGER_ENABLE 0x6
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#define SBI_EXT_DBTR_TRIGGER_DISABLE 0x7
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/** General pmu event codes specified in SBI PMU extension */
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enum sbi_pmu_hw_generic_events_t {
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SBI_PMU_HW_NO_EVENT = 0,
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SBI_PMU_HW_CPU_CYCLES = 1,
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SBI_PMU_HW_INSTRUCTIONS = 2,
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SBI_PMU_HW_CACHE_REFERENCES = 3,
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SBI_PMU_HW_CACHE_MISSES = 4,
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SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,
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SBI_PMU_HW_BRANCH_MISSES = 6,
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SBI_PMU_HW_BUS_CYCLES = 7,
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SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,
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SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,
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SBI_PMU_HW_REF_CPU_CYCLES = 10,
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SBI_PMU_HW_GENERAL_MAX,
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};
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/**
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* Generalized hardware cache events:
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*
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* { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
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* { read, write, prefetch } x
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* { accesses, misses }
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*/
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enum sbi_pmu_hw_cache_id {
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SBI_PMU_HW_CACHE_L1D = 0,
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SBI_PMU_HW_CACHE_L1I = 1,
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SBI_PMU_HW_CACHE_LL = 2,
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SBI_PMU_HW_CACHE_DTLB = 3,
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SBI_PMU_HW_CACHE_ITLB = 4,
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SBI_PMU_HW_CACHE_BPU = 5,
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SBI_PMU_HW_CACHE_NODE = 6,
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SBI_PMU_HW_CACHE_MAX,
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};
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enum sbi_pmu_hw_cache_op_id {
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SBI_PMU_HW_CACHE_OP_READ = 0,
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SBI_PMU_HW_CACHE_OP_WRITE = 1,
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SBI_PMU_HW_CACHE_OP_PREFETCH = 2,
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SBI_PMU_HW_CACHE_OP_MAX,
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};
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enum sbi_pmu_hw_cache_op_result_id {
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SBI_PMU_HW_CACHE_RESULT_ACCESS = 0,
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SBI_PMU_HW_CACHE_RESULT_MISS = 1,
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SBI_PMU_HW_CACHE_RESULT_MAX,
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};
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/**
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* Special "firmware" events provided by the OpenSBI, even if the hardware
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* does not support performance events. These events are encoded as a raw
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* event type in Linux kernel perf framework.
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*/
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enum sbi_pmu_fw_event_code_id {
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SBI_PMU_FW_MISALIGNED_LOAD = 0,
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SBI_PMU_FW_MISALIGNED_STORE = 1,
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SBI_PMU_FW_ACCESS_LOAD = 2,
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SBI_PMU_FW_ACCESS_STORE = 3,
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SBI_PMU_FW_ILLEGAL_INSN = 4,
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SBI_PMU_FW_SET_TIMER = 5,
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SBI_PMU_FW_IPI_SENT = 6,
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SBI_PMU_FW_IPI_RECVD = 7,
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SBI_PMU_FW_FENCE_I_SENT = 8,
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SBI_PMU_FW_FENCE_I_RECVD = 9,
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SBI_PMU_FW_SFENCE_VMA_SENT = 10,
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SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
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SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
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SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13,
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SBI_PMU_FW_HFENCE_GVMA_SENT = 14,
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SBI_PMU_FW_HFENCE_GVMA_RCVD = 15,
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SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
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SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
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SBI_PMU_FW_HFENCE_VVMA_SENT = 18,
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SBI_PMU_FW_HFENCE_VVMA_RCVD = 19,
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SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
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SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
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SBI_PMU_FW_MAX,
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/*
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* Event codes 22 to 255 are reserved for future use.
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* Event codes 256 to 65534 are reserved for SBI implementation
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* specific custom firmware events.
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*/
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SBI_PMU_FW_RESERVED_MAX = 0xFFFE,
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/*
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* Event code 0xFFFF is used for platform specific firmware
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* events where the event data contains any event specific information.
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*/
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SBI_PMU_FW_PLATFORM = 0xFFFF,
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};
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/** SBI PMU event idx type */
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enum sbi_pmu_event_type_id {
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SBI_PMU_EVENT_TYPE_HW = 0x0,
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SBI_PMU_EVENT_TYPE_HW_CACHE = 0x1,
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SBI_PMU_EVENT_TYPE_HW_RAW = 0x2,
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SBI_PMU_EVENT_TYPE_FW = 0xf,
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SBI_PMU_EVENT_TYPE_MAX,
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};
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/** SBI PMU counter type */
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enum sbi_pmu_ctr_type {
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SBI_PMU_CTR_TYPE_HW = 0,
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SBI_PMU_CTR_TYPE_FW,
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};
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/* Helper macros to decode event idx */
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#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
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#define SBI_PMU_EVENT_IDX_TYPE_OFFSET 16
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#define SBI_PMU_EVENT_IDX_TYPE_MASK (0xF << SBI_PMU_EVENT_IDX_TYPE_OFFSET)
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#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
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#define SBI_PMU_EVENT_RAW_IDX 0x20000
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#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
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#define SBI_PMU_EVENT_HW_CACHE_OPS_RESULT 0x1
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#define SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK 0x6
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#define SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET 1
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#define SBI_PMU_EVENT_HW_CACHE_ID_MASK 0xfff8
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#define SBI_PMU_EVENT_HW_CACHE_ID_OFFSET 3
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/* Flags defined for config matching function */
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#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0)
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#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1)
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#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2)
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#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3)
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#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4)
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#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5)
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#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6)
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#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7)
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/* Flags defined for counter start function */
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#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0)
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#define SBI_PMU_START_FLAG_INIT_FROM_SNAPSHOT (1 << 1)
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/* Flags defined for counter stop function */
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#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
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#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT (1 << 1)
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/* SBI function IDs for DBCN extension */
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#define SBI_EXT_DBCN_CONSOLE_WRITE 0x0
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#define SBI_EXT_DBCN_CONSOLE_READ 0x1
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#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
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/* SBI function IDs for SUSP extension */
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#define SBI_EXT_SUSP_SUSPEND 0x0
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#define SBI_SUSP_SLEEP_TYPE_SUSPEND 0x0
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#define SBI_SUSP_SLEEP_TYPE_LAST SBI_SUSP_SLEEP_TYPE_SUSPEND
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#define SBI_SUSP_PLATFORM_SLEEP_START 0x80000000
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/* SBI function IDs for CPPC extension */
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#define SBI_EXT_CPPC_PROBE 0x0
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#define SBI_EXT_CPPC_READ 0x1
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#define SBI_EXT_CPPC_READ_HI 0x2
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#define SBI_EXT_CPPC_WRITE 0x3
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enum sbi_cppc_reg_id {
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SBI_CPPC_HIGHEST_PERF = 0x00000000,
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SBI_CPPC_NOMINAL_PERF = 0x00000001,
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SBI_CPPC_LOW_NON_LINEAR_PERF = 0x00000002,
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SBI_CPPC_LOWEST_PERF = 0x00000003,
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SBI_CPPC_GUARANTEED_PERF = 0x00000004,
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SBI_CPPC_DESIRED_PERF = 0x00000005,
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SBI_CPPC_MIN_PERF = 0x00000006,
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SBI_CPPC_MAX_PERF = 0x00000007,
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SBI_CPPC_PERF_REDUC_TOLERANCE = 0x00000008,
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SBI_CPPC_TIME_WINDOW = 0x00000009,
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SBI_CPPC_CTR_WRAP_TIME = 0x0000000A,
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SBI_CPPC_REFERENCE_CTR = 0x0000000B,
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SBI_CPPC_DELIVERED_CTR = 0x0000000C,
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SBI_CPPC_PERF_LIMITED = 0x0000000D,
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SBI_CPPC_ENABLE = 0x0000000E,
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SBI_CPPC_AUTO_SEL_ENABLE = 0x0000000F,
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SBI_CPPC_AUTO_ACT_WINDOW = 0x00000010,
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SBI_CPPC_ENERGY_PERF_PREFERENCE = 0x00000011,
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SBI_CPPC_REFERENCE_PERF = 0x00000012,
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SBI_CPPC_LOWEST_FREQ = 0x00000013,
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SBI_CPPC_NOMINAL_FREQ = 0x00000014,
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SBI_CPPC_ACPI_LAST = SBI_CPPC_NOMINAL_FREQ,
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SBI_CPPC_TRANSITION_LATENCY = 0x80000000,
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SBI_CPPC_NON_ACPI_LAST = SBI_CPPC_TRANSITION_LATENCY,
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};
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/* SBI Function IDs for SSE extension */
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#define SBI_EXT_SSE_READ_ATTR 0x00000000
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#define SBI_EXT_SSE_WRITE_ATTR 0x00000001
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#define SBI_EXT_SSE_REGISTER 0x00000002
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#define SBI_EXT_SSE_UNREGISTER 0x00000003
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#define SBI_EXT_SSE_ENABLE 0x00000004
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#define SBI_EXT_SSE_DISABLE 0x00000005
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#define SBI_EXT_SSE_COMPLETE 0x00000006
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#define SBI_EXT_SSE_INJECT 0x00000007
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/* SBI SSE Event Attributes. */
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enum sbi_sse_attr_id {
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SBI_SSE_ATTR_STATUS = 0x00000000,
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SBI_SSE_ATTR_PRIO = 0x00000001,
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SBI_SSE_ATTR_CONFIG = 0x00000002,
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SBI_SSE_ATTR_PREFERRED_HART = 0x00000003,
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SBI_SSE_ATTR_ENTRY_PC = 0x00000004,
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SBI_SSE_ATTR_ENTRY_ARG = 0x00000005,
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SBI_SSE_ATTR_INTERRUPTED_SEPC = 0x00000006,
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SBI_SSE_ATTR_INTERRUPTED_FLAGS = 0x00000007,
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SBI_SSE_ATTR_INTERRUPTED_A6 = 0x00000008,
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SBI_SSE_ATTR_INTERRUPTED_A7 = 0x00000009,
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SBI_SSE_ATTR_MAX = 0x0000000A
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};
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#define SBI_SSE_ATTR_STATUS_STATE_OFFSET 0
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#define SBI_SSE_ATTR_STATUS_STATE_MASK 0x3
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#define SBI_SSE_ATTR_STATUS_PENDING_OFFSET 2
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#define SBI_SSE_ATTR_STATUS_INJECT_OFFSET 3
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#define SBI_SSE_ATTR_CONFIG_ONESHOT (1 << 0)
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#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_STATUS_SPP BIT(0)
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#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_STATUS_SPIE BIT(1)
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#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPV BIT(2)
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#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPVP BIT(3)
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enum sbi_sse_state {
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SBI_SSE_STATE_UNUSED = 0,
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SBI_SSE_STATE_REGISTERED = 1,
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SBI_SSE_STATE_ENABLED = 2,
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SBI_SSE_STATE_RUNNING = 3,
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};
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/* SBI SSE Event IDs. */
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#define SBI_SSE_EVENT_LOCAL_RAS 0x00000000
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#define SBI_SSE_EVENT_LOCAL_PLAT_0_START 0x00004000
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#define SBI_SSE_EVENT_LOCAL_PLAT_0_END 0x00007fff
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#define SBI_SSE_EVENT_GLOBAL_RAS 0x00008000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_0_START 0x00004000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_0_END 0x00007fff
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#define SBI_SSE_EVENT_LOCAL_PMU 0x00010000
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#define SBI_SSE_EVENT_LOCAL_PLAT_1_START 0x00014000
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#define SBI_SSE_EVENT_LOCAL_PLAT_1_END 0x00017fff
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#define SBI_SSE_EVENT_GLOBAL_PLAT_1_START 0x0001c000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_1_END 0x0001ffff
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#define SBI_SSE_EVENT_LOCAL_PLAT_2_START 0x00024000
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#define SBI_SSE_EVENT_LOCAL_PLAT_2_END 0x00027fff
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#define SBI_SSE_EVENT_GLOBAL_PLAT_2_START 0x0002c000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_2_END 0x0002ffff
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#define SBI_SSE_EVENT_LOCAL_SOFTWARE 0xffff0000
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#define SBI_SSE_EVENT_LOCAL_PLAT_3_START 0xffff4000
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#define SBI_SSE_EVENT_LOCAL_PLAT_3_END 0xffff7fff
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#define SBI_SSE_EVENT_GLOBAL_SOFTWARE 0xffff8000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_3_START 0xffffc000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_3_END 0xffffffff
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#define SBI_SSE_EVENT_GLOBAL_BIT (1 << 15)
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#define SBI_SSE_EVENT_PLATFORM_BIT (1 << 14)
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/* SBI base specification related macros */
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#define SBI_SPEC_VERSION_MAJOR_OFFSET 24
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#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
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#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
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#define SBI_EXT_VENDOR_START 0x09000000
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#define SBI_EXT_VENDOR_END 0x09FFFFFF
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#define SBI_EXT_FIRMWARE_START 0x0A000000
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#define SBI_EXT_FIRMWARE_END 0x0AFFFFFF
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/* SBI return error codes */
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#define SBI_SUCCESS 0
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#define SBI_ERR_FAILED -1
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#define SBI_ERR_NOT_SUPPORTED -2
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#define SBI_ERR_INVALID_PARAM -3
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#define SBI_ERR_DENIED -4
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#define SBI_ERR_INVALID_ADDRESS -5
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#define SBI_ERR_ALREADY_AVAILABLE -6
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#define SBI_ERR_ALREADY_STARTED -7
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#define SBI_ERR_ALREADY_STOPPED -8
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#define SBI_ERR_NO_SHMEM -9
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#define SBI_ERR_INVALID_STATE -10
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#define SBI_ERR_BAD_RANGE -11
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#define SBI_LAST_ERR SBI_ERR_BAD_RANGE
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/* clang-format on */
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#endif
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