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https://gitlab.com/qemu-project/qemu-palcode.git
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139 lines
2.8 KiB
ArmAsm
139 lines
2.8 KiB
ArmAsm
/* PALcode and C runtime functions for the CLIPPER system emulation.
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Copyright (C) 2011 Richard Henderson
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This file is part of QEMU PALcode.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the text
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of the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not see
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<http://www.gnu.org/licenses/>. */
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#include "pal.h"
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#include SYSTEM_H
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/*
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* Sys_Setup
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*
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* Do any system specific setup necessary.
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*
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* INPUT PARAMETERS
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*
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* a0 = whami
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* p7 = return address
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*/
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.globl Sys_Setup
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.ent Sys_Setup
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Sys_Setup:
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.frame $sp, 0, p7, 0
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LOAD_PHYS_CCHIP t0
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lda t0, TYPHOON_CCHIP_DIR0(t0)
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// DIR[23] differ from DIR[01] by 0x400
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// DIR[13] differ from DIR[02] by 0x40
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and a0, 2, t4
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and a0, 1, t3
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sll t4, 9, t4
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sll t3, 6, t3
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addq t0, t4, t0
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addq t0, t3, t0
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// IIC[0-4] differ from DIR[0-4] by 0x100
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lda t2, 0x100(t0)
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mtpr t0, ptCpuDIR
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mtpr t2, ptCpuIIC
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ret
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.end Sys_Setup
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/*
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* Sys_Dev_Vector
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*
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* Load the SRM interrupt vector for the system.
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*
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* INPUT PARAMETERS
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*
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* p7 = return address
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*
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* OUTPUT PARAMETERS
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*
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* a1 = interrupt vector
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*/
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.globl Sys_Dev_Vector
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.ent Sys_Dev_Vector
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Sys_Dev_Vector:
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.frame $sp, 0, p7, 0
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mfpr a1, ptCpuDIR // Load int mask for this CPU
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ldq_p a1, 0(a1)
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beq a1, CallPal_Rti // No interrupts asserted?
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cttz a1, a1 // Find the first asserted interrupt.
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cmpeq a1, 55, a0 // Is this an ISA interrupt?
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addq a1, 16, a1 // PCI interrupt numbers start at 16
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beq a0, 1f
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LOAD_PHYS_PCHIP0_IACK a1 // IACK results in the ISA irq
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ldl_p a1, 0(a1)
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1: sll a1, 4, a1
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lda a1, 0x800(a1)
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ret $31, (p7), 0
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.end Sys_Dev_Vector
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/*
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* Cserve_Ena
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*
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* Unmask a PCI interrupt
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*/
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.globl Cserve_Ena
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Cserve_Ena:
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// FIXME
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hw_rei
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ENDFN Cserve_Ena
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/*
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* Cserve_Dis
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*
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* Mask a PCI interrupt
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*/
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.globl Cserve_Dis
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Cserve_Dis:
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// FIXME
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hw_rei
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ENDFN Cserve_Dis
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/*
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* PCI parameters
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*/
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.section .sdata
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.align 3
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.globl pci_io_base
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.type pci_io_base, @object
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.size pci_io_base, 8
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pci_io_base:
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.quad PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_IO
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.globl pci_conf_base
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.type pci_conf_base, @object
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.size pci_conf_base, 8
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pci_conf_base:
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.quad PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_CONF
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.align 3
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.globl pci_mem_base
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.type pci_mem_base, @object
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.size pci_mem_base, 8
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pci_mem_base:
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.quad PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_MEM
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