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63070ce368
Update aarch64-core.xml to include field definitions for PSTATE, which in gdb is modelled in the cpsr (current program status register) pseudo-register, named after the actual cpsr register in armv7. Defining the fields layout of the register allows easy inspection of for example, the current exception level (EL): For example. Before booting a Linux guest, EL=2, but after booting and Ctrl-C'ing in gdb, we get EL=0: (gdb) info registers $cpsr cpsr 0x20402009 [ SP EL=2 BTYPE=0 PAN C ] (gdb) cont Continuing. ^C Thread 2 received signal SIGINT, Interrupt. 0x0000ffffaaff286c in ?? () (gdb) info registers $cpsr cpsr 0x20001000 [ EL=0 BTYPE=0 SSBS C ] The aarch64-core.xml has been updated to match exactly the version retrieved from upstream gdb, retrieved in 2025-05-19 from HEAD commit 9f4dc0b137c86f6ff2098cb1ab69442c69d6023d. Link: https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gdb/features/aarch64-core.xml;h=b8046510b9a085d30463d37b3ecc8d435f5fb7a4;hb=HEAD Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-Id: <20250519-gdbstub-aarch64-pstate-xml-v1-1-b4dbe87fe7c6@linaro.org> [AJB: expanded upstream link] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250603110204.838117-18-alex.bennee@linaro.org>
95 lines
3.1 KiB
XML
95 lines
3.1 KiB
XML
<?xml version="1.0"?>
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<!-- Copyright (C) 2009-2025 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.aarch64.core">
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<reg name="x0" bitsize="64"/>
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<reg name="x1" bitsize="64"/>
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<reg name="x2" bitsize="64"/>
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<reg name="x3" bitsize="64"/>
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<reg name="x4" bitsize="64"/>
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<reg name="x5" bitsize="64"/>
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<reg name="x6" bitsize="64"/>
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<reg name="x7" bitsize="64"/>
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<reg name="x8" bitsize="64"/>
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<reg name="x9" bitsize="64"/>
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<reg name="x10" bitsize="64"/>
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<reg name="x11" bitsize="64"/>
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<reg name="x12" bitsize="64"/>
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<reg name="x13" bitsize="64"/>
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<reg name="x14" bitsize="64"/>
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<reg name="x15" bitsize="64"/>
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<reg name="x16" bitsize="64"/>
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<reg name="x17" bitsize="64"/>
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<reg name="x18" bitsize="64"/>
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<reg name="x19" bitsize="64"/>
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<reg name="x20" bitsize="64"/>
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<reg name="x21" bitsize="64"/>
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<reg name="x22" bitsize="64"/>
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<reg name="x23" bitsize="64"/>
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<reg name="x24" bitsize="64"/>
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<reg name="x25" bitsize="64"/>
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<reg name="x26" bitsize="64"/>
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<reg name="x27" bitsize="64"/>
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<reg name="x28" bitsize="64"/>
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<reg name="x29" bitsize="64"/>
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<reg name="x30" bitsize="64"/>
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<reg name="sp" bitsize="64" type="data_ptr"/>
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<reg name="pc" bitsize="64" type="code_ptr"/>
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<flags id="cpsr_flags" size="4">
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<!-- Stack Pointer. -->
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<field name="SP" start="0" end="0"/>
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<!-- Exception Level. -->
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<field name="EL" start="2" end="3"/>
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<!-- Execution state. -->
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<field name="nRW" start="4" end="4"/>
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<!-- FIQ interrupt mask. -->
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<field name="F" start="6" end="6"/>
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<!-- IRQ interrupt mask. -->
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<field name="I" start="7" end="7"/>
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<!-- SError interrupt mask. -->
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<field name="A" start="8" end="8"/>
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<!-- Debug exception mask. -->
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<field name="D" start="9" end="9"/>
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<!-- ARMv8.5-A: Branch Target Identification BTYPE. -->
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<field name="BTYPE" start="10" end="11"/>
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<!-- ARMv8.0-A: Speculative Store Bypass. -->
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<field name="SSBS" start="12" end="12"/>
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<!-- Illegal Execution state. -->
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<field name="IL" start="20" end="20"/>
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<!-- Software Step. -->
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<field name="SS" start="21" end="21"/>
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<!-- ARMv8.1-A: Privileged Access Never. -->
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<field name="PAN" start="22" end="22"/>
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<!-- ARMv8.2-A: User Access Override. -->
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<field name="UAO" start="23" end="23"/>
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<!-- ARMv8.4-A: Data Independent Timing. -->
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<field name="DIT" start="24" end="24"/>
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<!-- ARMv8.5-A: Tag Check Override. -->
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<field name="TCO" start="25" end="25"/>
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<!-- Overflow Condition flag. -->
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<field name="V" start="28" end="28"/>
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<!-- Carry Condition flag. -->
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<field name="C" start="29" end="29"/>
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<!-- Zero Condition flag. -->
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<field name="Z" start="30" end="30"/>
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<!-- Negative Condition flag. -->
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<field name="N" start="31" end="31"/>
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</flags>
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<reg name="cpsr" bitsize="32" type="cpsr_flags"/>
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</feature>
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